MIPS: Cleaned up CpuFeature scope handling.

test/cctest/test-assembler-mips.cc

 // Copyright 2012 the V8 project authors. All rights reserved.
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions are
 // met:
 //
 //     * Redistributions of source code must retain the above copyright
 //       notice, this list of conditions and the following disclaimer.
 //     * Redistributions in binary form must reproduce the above
 //       copyright notice, this list of conditions and the following
 //       disclaimer in the documentation and/or other materials provided
@@ skipping 269 matching lines @@
     double i;
   } T;
   T t;
 
   // Create a function that accepts &t, and loads, manipulates, and stores
   // the doubles t.a ... t.f.
   MacroAssembler assm(Isolate::Current(), NULL, 0);
   Label L, C;
 
   if (CpuFeatures::IsSupported(FPU)) {
-    CpuFeatures::Scope scope(FPU);
+    CpuFeatureScope scope(&assm, FPU);
 
     __ ldc1(f4, MemOperand(a0, OFFSET_OF(T, a)) );
     __ ldc1(f6, MemOperand(a0, OFFSET_OF(T, b)) );
     __ add_d(f8, f4, f6);
     __ sdc1(f8, MemOperand(a0, OFFSET_OF(T, c)) );  // c = a + b.
 
     __ mov_d(f10, f8);  // c
     __ neg_d(f12, f6);  // -b
     __ sub_d(f10, f10, f12);
     __ sdc1(f10, MemOperand(a0, OFFSET_OF(T, d)) );  // d = c - (-b).
@@ skipping 62 matching lines @@
     double a;
     double b;
     double c;
   } T;
   T t;
 
   Assembler assm(Isolate::Current(), NULL, 0);
   Label L, C;
 
   if (CpuFeatures::IsSupported(FPU)) {
-    CpuFeatures::Scope scope(FPU);
+    CpuFeatureScope scope(&assm, FPU);
 
     __ ldc1(f4, MemOperand(a0, OFFSET_OF(T, a)) );
     __ ldc1(f6, MemOperand(a0, OFFSET_OF(T, b)) );
 
     // Swap f4 and f6, by using four integer registers, t0-t3.
     __ mfc1(t0, f4);
     __ mfc1(t1, f5);
     __ mfc1(t2, f6);
     __ mfc1(t3, f7);
 
@@ skipping 40 matching lines @@
     double b;
     int i;
     int j;
   } T;
   T t;
 
   Assembler assm(Isolate::Current(), NULL, 0);
   Label L, C;
 
   if (CpuFeatures::IsSupported(FPU)) {
-    CpuFeatures::Scope scope(FPU);
+    CpuFeatureScope scope(&assm, FPU);
 
     // Load all structure elements to registers.
     __ ldc1(f4, MemOperand(a0, OFFSET_OF(T, a)) );
     __ ldc1(f6, MemOperand(a0, OFFSET_OF(T, b)) );
     __ lw(t0, MemOperand(a0, OFFSET_OF(T, i)) );
     __ lw(t1, MemOperand(a0, OFFSET_OF(T, j)) );
 
     // Convert double in f4 to int in element i.
     __ cvt_w_d(f8, f4);
     __ mfc1(t2, f8);
@@ skipping 127 matching lines @@
     int32_t result;
   } T;
   T t;
 
   // Create a function that accepts &t, and loads, manipulates, and stores
   // the doubles t.a ... t.f.
   MacroAssembler assm(Isolate::Current(), NULL, 0);
   Label neither_is_nan, less_than, outa_here;
 
   if (CpuFeatures::IsSupported(FPU)) {
-    CpuFeatures::Scope scope(FPU);
+    CpuFeatureScope scope(&assm, FPU);
 
     __ ldc1(f4, MemOperand(a0, OFFSET_OF(T, a)) );
     __ ldc1(f6, MemOperand(a0, OFFSET_OF(T, b)) );
     __ c(UN, D, f4, f6);
     __ bc1f(&neither_is_nan);
     __ nop();
     __ sw(zero_reg, MemOperand(a0, OFFSET_OF(T, result)) );
     __ Branch(&outa_here);
 
     __ bind(&neither_is_nan);
@@ skipping 192 matching lines @@
     int32_t long_lo;
     int32_t b_long_hi;
     int32_t b_long_lo;
   } T;
   T t;
 
   Assembler assm(Isolate::Current(), NULL, 0);
   Label L, C;
 
   if (CpuFeatures::IsSupported(FPU) && kArchVariant == kMips32r2) {
-    CpuFeatures::Scope scope(FPU);
+    CpuFeatureScope scope(&assm, FPU);
 
     // Load all structure elements to registers.
     __ ldc1(f0, MemOperand(a0, OFFSET_OF(T, a)));
 
     // Save the raw bits of the double.
     __ mfc1(t0, f0);
     __ mfc1(t1, f1);
     __ sw(t0, MemOperand(a0, OFFSET_OF(T, dbl_mant)));
     __ sw(t1, MemOperand(a0, OFFSET_OF(T, dbl_exp)));
 
@@ skipping 284 matching lines @@
     uint32_t trunc_big_out;
     uint32_t trunc_small_out;
     uint32_t cvt_big_in;
     uint32_t cvt_small_in;
   } T;
   T t;
 
   MacroAssembler assm(Isolate::Current(), NULL, 0);
 
   if (CpuFeatures::IsSupported(FPU)) {
-    CpuFeatures::Scope scope(FPU);
+    CpuFeatureScope scope(&assm, FPU);
 
     __ sw(t0, MemOperand(a0, OFFSET_OF(T, cvt_small_in)));
     __ Cvt_d_uw(f10, t0, f22);
     __ sdc1(f10, MemOperand(a0, OFFSET_OF(T, cvt_small_out)));
 
     __ Trunc_uw_d(f10, f10, f22);
     __ swc1(f10, MemOperand(a0, OFFSET_OF(T, trunc_small_out)));
 
     __ sw(t0, MemOperand(a0, OFFSET_OF(T, cvt_big_in)));
     __ Cvt_d_uw(f8, t0, f22);
@@ skipping 62 matching lines @@
     ROUND_STRUCT_ELEMENT(trunc)
     ROUND_STRUCT_ELEMENT(cvt)
   } T;
   T t;
 
 #undef ROUND_STRUCT_ELEMENT
 
   MacroAssembler assm(Isolate::Current(), NULL, 0);
 
   if (CpuFeatures::IsSupported(FPU)) {
-    CpuFeatures::Scope scope(FPU);
+    CpuFeatureScope scope(&assm, FPU);
 
     // Save FCSR.
     __ cfc1(a1, FCSR);
     // Disable FPU exceptions.
     __ ctc1(zero_reg, FCSR);
 #define RUN_ROUND_TEST(x) \
     __ ldc1(f0, MemOperand(a0, OFFSET_OF(T, round_up_in))); \
     __ x##_w_d(f0, f0); \
     __ swc1(f0, MemOperand(a0, OFFSET_OF(T, x##_up_out))); \
     \
@@ skipping 92 matching lines @@
   Label target;
   __ beq(v0, v1, &target);
   __ nop();
   __ bne(v0, v1, &target);
   __ nop();
   __ bind(&target);
   __ nop();
 }
 
 #undef __