[turbofan]: Elide extra move when accessing stack or frame register

src/compiler/arm/code-generator-arm.cc

Index: src/compiler/arm/code-generator-arm.cc
diff --git a/src/compiler/arm/code-generator-arm.cc b/src/compiler/arm/code-generator-arm.cc
index 0c97f846f0cff35eaccb09b24a02ca10f81dcca5..3e499ea62667090f68955330a8139d3e74b19e2f 100644
--- a/src/compiler/arm/code-generator-arm.cc
+++ b/src/compiler/arm/code-generator-arm.cc
@@ -147,7 +147,7 @@ class ArmOperandConverter final : public InstructionOperandConverter {
 
   MemOperand ToMemOperand(InstructionOperand* op) const {
     DCHECK(op != NULL);
-    DCHECK(!op->IsRegister());
+    DCHECK(!op->GeneratesRegister());
     DCHECK(!op->IsDoubleRegister());
     DCHECK(op->IsStackSlot() || op->IsDoubleStackSlot());
     // The linkage computes where all spill slots are located.
@@ -241,7 +241,7 @@ Condition FlagsConditionToCondition(FlagsCondition condition) {
   do {                                                               \
     auto result = i.OutputFloat##width##Register();                  \
     auto offset = i.InputRegister(0);                                \
-    if (instr->InputAt(1)->IsRegister()) {                           \
+    if (instr->InputAt(1)->GeneratesRegister()) {                    \
       __ cmp(offset, i.InputRegister(1));                            \
     } else {                                                         \
       __ cmp(offset, i.InputImmediate(1));                           \
@@ -258,7 +258,7 @@ Condition FlagsConditionToCondition(FlagsCondition condition) {
   do {                                                          \
     auto result = i.OutputRegister();                           \
     auto offset = i.InputRegister(0);                           \
-    if (instr->InputAt(1)->IsRegister()) {                      \
+    if (instr->InputAt(1)->GeneratesRegister()) {               \
       __ cmp(offset, i.InputRegister(1));                       \
     } else {                                                    \
       __ cmp(offset, i.InputImmediate(1));                      \
@@ -274,7 +274,7 @@ Condition FlagsConditionToCondition(FlagsCondition condition) {
 #define ASSEMBLE_CHECKED_STORE_FLOAT(width)        \
   do {                                             \
     auto offset = i.InputRegister(0);              \
-    if (instr->InputAt(1)->IsRegister()) {         \
+    if (instr->InputAt(1)->GeneratesRegister()) {  \
       __ cmp(offset, i.InputRegister(1));          \
     } else {                                       \
       __ cmp(offset, i.InputImmediate(1));         \
@@ -288,7 +288,7 @@ Condition FlagsConditionToCondition(FlagsCondition condition) {
 #define ASSEMBLE_CHECKED_STORE_INTEGER(asm_instr) \
   do {                                            \
     auto offset = i.InputRegister(0);             \
-    if (instr->InputAt(1)->IsRegister()) {        \
+    if (instr->InputAt(1)->GeneratesRegister()) { \
       __ cmp(offset, i.InputRegister(1));         \
     } else {                                      \
       __ cmp(offset, i.InputImmediate(1));        \
@@ -1070,18 +1070,18 @@ void CodeGenerator::AssembleMove(InstructionOperand* source,
   ArmOperandConverter g(this, NULL);
   // Dispatch on the source and destination operand kinds.  Not all
   // combinations are possible.
-  if (source->IsRegister()) {
-    DCHECK(destination->IsRegister() || destination->IsStackSlot());
+  if (source->GeneratesRegister()) {
+    DCHECK(destination->GeneratesRegister() || destination->IsStackSlot());
     Register src = g.ToRegister(source);
-    if (destination->IsRegister()) {
+    if (destination->GeneratesRegister()) {
       __ mov(g.ToRegister(destination), src);
     } else {
       __ str(src, g.ToMemOperand(destination));
     }
   } else if (source->IsStackSlot()) {
-    DCHECK(destination->IsRegister() || destination->IsStackSlot());
+    DCHECK(destination->GeneratesRegister() || destination->IsStackSlot());
     MemOperand src = g.ToMemOperand(source);
-    if (destination->IsRegister()) {
+    if (destination->GeneratesRegister()) {
       __ ldr(g.ToRegister(destination), src);
     } else {
       Register temp = kScratchReg;
@@ -1090,9 +1090,10 @@ void CodeGenerator::AssembleMove(InstructionOperand* source,
     }
   } else if (source->IsConstant()) {
     Constant src = g.ToConstant(source);
-    if (destination->IsRegister() || destination->IsStackSlot()) {
-      Register dst =
-          destination->IsRegister() ? g.ToRegister(destination) : kScratchReg;
+    if (destination->GeneratesRegister() || destination->IsStackSlot()) {
+      Register dst = destination->GeneratesRegister()
+                         ? g.ToRegister(destination)
+                         : kScratchReg;
       switch (src.type()) {
         case Constant::kInt32:
           __ mov(dst, Operand(src.ToInt32()));
@@ -1178,11 +1179,11 @@ void CodeGenerator::AssembleSwap(InstructionOperand* source,
   ArmOperandConverter g(this, NULL);
   // Dispatch on the source and destination operand kinds.  Not all
   // combinations are possible.
-  if (source->IsRegister()) {
+  if (source->GeneratesRegister()) {
     // Register-register.
     Register temp = kScratchReg;
     Register src = g.ToRegister(source);
-    if (destination->IsRegister()) {
+    if (destination->GeneratesRegister()) {
       Register dst = g.ToRegister(destination);
       __ Move(temp, src);
       __ Move(src, dst);