[turbofan]: Elide extra move when accessing stack or frame register

src/compiler/mips64/code-generator-mips64.cc

 // Copyright 2014 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 #include "src/compiler/code-generator.h"
 #include "src/compiler/code-generator-impl.h"
 #include "src/compiler/gap-resolver.h"
 #include "src/compiler/node-matchers.h"
 #include "src/mips/macro-assembler-mips.h"
 #include "src/scopes.h"
@@ skipping 62 matching lines @@
       case Constant::kRpoNumber:
         UNREACHABLE();  // TODO(titzer): RPO immediates on mips?
         break;
     }
     UNREACHABLE();
     return Operand(zero_reg);
   }
 
   Operand InputOperand(size_t index) {
     InstructionOperand* op = instr_->InputAt(index);
-    if (op->IsRegister()) {
+    if (op->GeneratesRegister()) {
       return Operand(ToRegister(op));
     }
     return InputImmediate(index);
   }
 
   MemOperand MemoryOperand(size_t* first_index) {
     const size_t index = *first_index;
     switch (AddressingModeField::decode(instr_->opcode())) {
       case kMode_None:
         break;
       case kMode_MRI:
         *first_index += 2;
         return MemOperand(InputRegister(index + 0), InputInt32(index + 1));
       case kMode_MRR:
         // TODO(plind): r6 address mode, to be implemented ...
         UNREACHABLE();
     }
     UNREACHABLE();
     return MemOperand(no_reg);
   }
 
   MemOperand MemoryOperand(size_t index = 0) { return MemoryOperand(&index); }
 
   MemOperand ToMemOperand(InstructionOperand* op) const {
     DCHECK(op != NULL);
-    DCHECK(!op->IsRegister());
+    DCHECK(!op->GeneratesRegister());
     DCHECK(!op->IsDoubleRegister());
     DCHECK(op->IsStackSlot() || op->IsDoubleStackSlot());
     // The linkage computes where all spill slots are located.
     FrameOffset offset = linkage()->GetFrameOffset(
         AllocatedOperand::cast(op)->index(), frame(), 0);
     return MemOperand(offset.from_stack_pointer() ? sp : fp, offset.offset());
   }
 };
 
 
 static inline bool HasRegisterInput(Instruction* instr, size_t index) {
-  return instr->InputAt(index)->IsRegister();
+  return instr->InputAt(index)->GeneratesRegister();
 }
 
 
 namespace {
 
 class OutOfLineLoadSingle final : public OutOfLineCode {
  public:
   OutOfLineLoadSingle(CodeGenerator* gen, FloatRegister result)
       : OutOfLineCode(gen), result_(result) {}
 
@@ skipping 165 matching lines @@
   return kNoFPUCondition;
 }
 
 }  // namespace
 
 
 #define ASSEMBLE_CHECKED_LOAD_FLOAT(width, asm_instr)                         \
   do {                                                                        \
     auto result = i.Output##width##Register();                                \
     auto ool = new (zone()) OutOfLineLoad##width(this, result);               \
-    if (instr->InputAt(0)->IsRegister()) {                                    \
+    if (instr->InputAt(0)->GeneratesRegister()) {                             \
       auto offset = i.InputRegister(0);                                       \
       __ Branch(USE_DELAY_SLOT, ool->entry(), hs, offset, i.InputOperand(1)); \
       __ Daddu(at, i.InputRegister(2), offset);                               \
       __ asm_instr(result, MemOperand(at, 0));                                \
     } else {                                                                  \
       int offset = static_cast<int>(i.InputOperand(0).immediate());           \
       __ Branch(ool->entry(), ls, i.InputRegister(1), Operand(offset));       \
       __ asm_instr(result, MemOperand(i.InputRegister(2), offset));           \
     }                                                                         \
     __ bind(ool->exit());                                                     \
   } while (0)
 
 
 #define ASSEMBLE_CHECKED_LOAD_INTEGER(asm_instr)                              \
   do {                                                                        \
     auto result = i.OutputRegister();                                         \
     auto ool = new (zone()) OutOfLineLoadInteger(this, result);               \
-    if (instr->InputAt(0)->IsRegister()) {                                    \
+    if (instr->InputAt(0)->GeneratesRegister()) {                             \
       auto offset = i.InputRegister(0);                                       \
       __ Branch(USE_DELAY_SLOT, ool->entry(), hs, offset, i.InputOperand(1)); \
       __ Daddu(at, i.InputRegister(2), offset);                               \
       __ asm_instr(result, MemOperand(at, 0));                                \
     } else {                                                                  \
       int offset = static_cast<int>(i.InputOperand(0).immediate());           \
       __ Branch(ool->entry(), ls, i.InputRegister(1), Operand(offset));       \
       __ asm_instr(result, MemOperand(i.InputRegister(2), offset));           \
     }                                                                         \
     __ bind(ool->exit());                                                     \
   } while (0)
 
 
 #define ASSEMBLE_CHECKED_STORE_FLOAT(width, asm_instr)                 \
   do {                                                                 \
     Label done;                                                        \
-    if (instr->InputAt(0)->IsRegister()) {                             \
+    if (instr->InputAt(0)->GeneratesRegister()) {                      \
       auto offset = i.InputRegister(0);                                \
       auto value = i.Input##width##Register(2);                        \
       __ Branch(USE_DELAY_SLOT, &done, hs, offset, i.InputOperand(1)); \
       __ Daddu(at, i.InputRegister(3), offset);                        \
       __ asm_instr(value, MemOperand(at, 0));                          \
     } else {                                                           \
       int offset = static_cast<int>(i.InputOperand(0).immediate());    \
       auto value = i.Input##width##Register(2);                        \
       __ Branch(&done, ls, i.InputRegister(1), Operand(offset));       \
       __ asm_instr(value, MemOperand(i.InputRegister(3), offset));     \
     }                                                                  \
     __ bind(&done);                                                    \
   } while (0)
 
 
 #define ASSEMBLE_CHECKED_STORE_INTEGER(asm_instr)                      \
   do {                                                                 \
     Label done;                                                        \
-    if (instr->InputAt(0)->IsRegister()) {                             \
+    if (instr->InputAt(0)->GeneratesRegister()) {                      \
       auto offset = i.InputRegister(0);                                \
       auto value = i.InputRegister(2);                                 \
       __ Branch(USE_DELAY_SLOT, &done, hs, offset, i.InputOperand(1)); \
       __ Daddu(at, i.InputRegister(3), offset);                        \
       __ asm_instr(value, MemOperand(at, 0));                          \
     } else {                                                           \
       int offset = static_cast<int>(i.InputOperand(0).immediate());    \
       auto value = i.InputRegister(2);                                 \
       __ Branch(&done, ls, i.InputRegister(1), Operand(offset));       \
       __ asm_instr(value, MemOperand(i.InputRegister(3), offset));     \
@@ skipping 189 matching lines @@
     case kMips64Or:
       __ Or(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1));
       break;
     case kMips64Xor:
       __ Xor(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1));
       break;
     case kMips64Clz:
       __ Clz(i.OutputRegister(), i.InputRegister(0));
       break;
     case kMips64Shl:
-      if (instr->InputAt(1)->IsRegister()) {
+      if (instr->InputAt(1)->GeneratesRegister()) {
         __ sllv(i.OutputRegister(), i.InputRegister(0), i.InputRegister(1));
       } else {
         int64_t imm = i.InputOperand(1).immediate();
         __ sll(i.OutputRegister(), i.InputRegister(0),
                static_cast<uint16_t>(imm));
       }
       break;
     case kMips64Shr:
-      if (instr->InputAt(1)->IsRegister()) {
+      if (instr->InputAt(1)->GeneratesRegister()) {
         __ srlv(i.OutputRegister(), i.InputRegister(0), i.InputRegister(1));
       } else {
         int64_t imm = i.InputOperand(1).immediate();
         __ srl(i.OutputRegister(), i.InputRegister(0),
                static_cast<uint16_t>(imm));
       }
       break;
     case kMips64Sar:
-      if (instr->InputAt(1)->IsRegister()) {
+      if (instr->InputAt(1)->GeneratesRegister()) {
         __ srav(i.OutputRegister(), i.InputRegister(0), i.InputRegister(1));
       } else {
         int64_t imm = i.InputOperand(1).immediate();
         __ sra(i.OutputRegister(), i.InputRegister(0),
                static_cast<uint16_t>(imm));
       }
       break;
     case kMips64Ext:
       __ Ext(i.OutputRegister(), i.InputRegister(0), i.InputInt8(1),
              i.InputInt8(2));
       break;
     case kMips64Dext:
       __ Dext(i.OutputRegister(), i.InputRegister(0), i.InputInt8(1),
               i.InputInt8(2));
       break;
     case kMips64Dshl:
-      if (instr->InputAt(1)->IsRegister()) {
+      if (instr->InputAt(1)->GeneratesRegister()) {
         __ dsllv(i.OutputRegister(), i.InputRegister(0), i.InputRegister(1));
       } else {
         int64_t imm = i.InputOperand(1).immediate();
         if (imm < 32) {
           __ dsll(i.OutputRegister(), i.InputRegister(0),
                   static_cast<uint16_t>(imm));
         } else {
           __ dsll32(i.OutputRegister(), i.InputRegister(0),
                     static_cast<uint16_t>(imm - 32));
         }
       }
       break;
     case kMips64Dshr:
-      if (instr->InputAt(1)->IsRegister()) {
+      if (instr->InputAt(1)->GeneratesRegister()) {
         __ dsrlv(i.OutputRegister(), i.InputRegister(0), i.InputRegister(1));
       } else {
         int64_t imm = i.InputOperand(1).immediate();
         if (imm < 32) {
           __ dsrl(i.OutputRegister(), i.InputRegister(0),
                   static_cast<uint16_t>(imm));
         } else {
           __ dsrl32(i.OutputRegister(), i.InputRegister(0),
                     static_cast<uint16_t>(imm - 32));
         }
       }
       break;
     case kMips64Dsar:
-      if (instr->InputAt(1)->IsRegister()) {
+      if (instr->InputAt(1)->GeneratesRegister()) {
         __ dsrav(i.OutputRegister(), i.InputRegister(0), i.InputRegister(1));
       } else {
         int64_t imm = i.InputOperand(1).immediate();
         if (imm < 32) {
           __ dsra(i.OutputRegister(), i.InputRegister(0), imm);
         } else {
           __ dsra32(i.OutputRegister(), i.InputRegister(0), imm - 32);
         }
       }
       break;
@@ skipping 598 matching lines @@
     __ Ret();
   }
 }
 
 
 void CodeGenerator::AssembleMove(InstructionOperand* source,
                                  InstructionOperand* destination) {
   MipsOperandConverter g(this, NULL);
   // Dispatch on the source and destination operand kinds.  Not all
   // combinations are possible.
-  if (source->IsRegister()) {
-    DCHECK(destination->IsRegister() || destination->IsStackSlot());
+  if (source->GeneratesRegister()) {
+    DCHECK(destination->GeneratesRegister() || destination->IsStackSlot());
     Register src = g.ToRegister(source);
-    if (destination->IsRegister()) {
+    if (destination->GeneratesRegister()) {
       __ mov(g.ToRegister(destination), src);
     } else {
       __ sd(src, g.ToMemOperand(destination));
     }
   } else if (source->IsStackSlot()) {
-    DCHECK(destination->IsRegister() || destination->IsStackSlot());
+    DCHECK(destination->GeneratesRegister() || destination->IsStackSlot());
     MemOperand src = g.ToMemOperand(source);
-    if (destination->IsRegister()) {
+    if (destination->GeneratesRegister()) {
       __ ld(g.ToRegister(destination), src);
     } else {
       Register temp = kScratchReg;
       __ ld(temp, src);
       __ sd(temp, g.ToMemOperand(destination));
     }
   } else if (source->IsConstant()) {
     Constant src = g.ToConstant(source);
-    if (destination->IsRegister() || destination->IsStackSlot()) {
-      Register dst =
-          destination->IsRegister() ? g.ToRegister(destination) : kScratchReg;
+    if (destination->GeneratesRegister() || destination->IsStackSlot()) {
+      Register dst = destination->GeneratesRegister()
+                         ? g.ToRegister(destination)
+                         : kScratchReg;
       switch (src.type()) {
         case Constant::kInt32:
           __ li(dst, Operand(src.ToInt32()));
           break;
         case Constant::kFloat32:
           __ li(dst, isolate()->factory()->NewNumber(src.ToFloat32(), TENURED));
           break;
         case Constant::kInt64:
           __ li(dst, Operand(src.ToInt64()));
           break;
@@ skipping 63 matching lines @@
     UNREACHABLE();
   }
 }
 
 
 void CodeGenerator::AssembleSwap(InstructionOperand* source,
                                  InstructionOperand* destination) {
   MipsOperandConverter g(this, NULL);
   // Dispatch on the source and destination operand kinds.  Not all
   // combinations are possible.
-  if (source->IsRegister()) {
+  if (source->GeneratesRegister()) {
     // Register-register.
     Register temp = kScratchReg;
     Register src = g.ToRegister(source);
-    if (destination->IsRegister()) {
+    if (destination->GeneratesRegister()) {
       Register dst = g.ToRegister(destination);
       __ Move(temp, src);
       __ Move(src, dst);
       __ Move(dst, temp);
     } else {
       DCHECK(destination->IsStackSlot());
       MemOperand dst = g.ToMemOperand(destination);
       __ mov(temp, src);
       __ ld(src, dst);
       __ sd(temp, dst);
@@ skipping 75 matching lines @@
       }
     }
   }
 }
 
 #undef __
 
 }  // namespace compiler
 }  // namespace internal
 }  // namespace v8