[turbofan]: Elide extra move when accessing stack or frame register

src/compiler/arm64/code-generator-arm64.cc

 // Copyright 2014 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 #include "src/compiler/code-generator.h"
 
 #include "src/arm64/macro-assembler-arm64.h"
 #include "src/compiler/code-generator-impl.h"
 #include "src/compiler/gap-resolver.h"
 #include "src/compiler/node-matchers.h"
@@ skipping 126 matching lines @@
     }
     UNREACHABLE();
     return MemOperand(no_reg);
   }
 
   MemOperand MemoryOperand(size_t first_index = 0) {
     return MemoryOperand(&first_index);
   }
 
   Operand ToOperand(InstructionOperand* op) {
-    if (op->IsRegister()) {
+    if (op->GeneratesRegister()) {
       return Operand(ToRegister(op));
     }
     return ToImmediate(op);
   }
 
   Operand ToOperand32(InstructionOperand* op) {
-    if (op->IsRegister()) {
+    if (op->GeneratesRegister()) {
       return Operand(ToRegister(op).W());
     }
     return ToImmediate(op);
   }
 
   Operand ToImmediate(InstructionOperand* operand) {
     Constant constant = ToConstant(operand);
     switch (constant.type()) {
       case Constant::kInt32:
         return Operand(constant.ToInt32());
@@ skipping 12 matching lines @@
       case Constant::kRpoNumber:
         UNREACHABLE();  // TODO(dcarney): RPO immediates on arm64.
         break;
     }
     UNREACHABLE();
     return Operand(-1);
   }
 
   MemOperand ToMemOperand(InstructionOperand* op, MacroAssembler* masm) const {
     DCHECK(op != NULL);
-    DCHECK(!op->IsRegister());
+    DCHECK(!op->GeneratesRegister());
     DCHECK(!op->IsDoubleRegister());
     DCHECK(op->IsStackSlot() || op->IsDoubleStackSlot());
     // The linkage computes where all spill slots are located.
     FrameOffset offset = linkage()->GetFrameOffset(
         AllocatedOperand::cast(op)->index(), frame(), 0);
     return MemOperand(offset.from_stack_pointer() ? masm->StackPointer() : fp,
                       offset.offset());
   }
 };
 
@@ skipping 128 matching lines @@
     __ Cmp(offset, length);                                \
     Label done;                                            \
     __ B(hs, &done);                                       \
     __ asm_instr(value, MemOperand(buffer, offset, UXTW)); \
     __ Bind(&done);                                        \
   } while (0)
 
 
 #define ASSEMBLE_SHIFT(asm_instr, width)                                    \
   do {                                                                      \
-    if (instr->InputAt(1)->IsRegister()) {                                  \
+    if (instr->InputAt(1)->GeneratesRegister()) {                           \
       __ asm_instr(i.OutputRegister##width(), i.InputRegister##width(0),    \
                    i.InputRegister##width(1));                              \
     } else {                                                                \
       uint32_t imm =                                                        \
           static_cast<uint32_t>(i.InputOperand##width(1).ImmediateValue()); \
       __ asm_instr(i.OutputRegister##width(), i.InputRegister##width(0),    \
                    imm % (width));                                          \
     }                                                                       \
   } while (0)
 
@@ skipping 845 matching lines @@
     __ Ret();
   }
 }
 
 
 void CodeGenerator::AssembleMove(InstructionOperand* source,
                                  InstructionOperand* destination) {
   Arm64OperandConverter g(this, NULL);
   // Dispatch on the source and destination operand kinds.  Not all
   // combinations are possible.
-  if (source->IsRegister()) {
-    DCHECK(destination->IsRegister() || destination->IsStackSlot());
+  if (source->GeneratesRegister()) {
+    DCHECK(destination->GeneratesRegister() || destination->IsStackSlot());
     Register src = g.ToRegister(source);
-    if (destination->IsRegister()) {
+    if (destination->GeneratesRegister()) {
       __ Mov(g.ToRegister(destination), src);
     } else {
       __ Str(src, g.ToMemOperand(destination, masm()));
     }
   } else if (source->IsStackSlot()) {
     MemOperand src = g.ToMemOperand(source, masm());
-    DCHECK(destination->IsRegister() || destination->IsStackSlot());
-    if (destination->IsRegister()) {
+    DCHECK(destination->GeneratesRegister() || destination->IsStackSlot());
+    if (destination->GeneratesRegister()) {
       __ Ldr(g.ToRegister(destination), src);
     } else {
       UseScratchRegisterScope scope(masm());
       Register temp = scope.AcquireX();
       __ Ldr(temp, src);
       __ Str(temp, g.ToMemOperand(destination, masm()));
     }
   } else if (source->IsConstant()) {
     Constant src = g.ToConstant(ConstantOperand::cast(source));
-    if (destination->IsRegister() || destination->IsStackSlot()) {
+    if (destination->GeneratesRegister() || destination->IsStackSlot()) {
       UseScratchRegisterScope scope(masm());
-      Register dst = destination->IsRegister() ? g.ToRegister(destination)
-                                               : scope.AcquireX();
+      Register dst = destination->GeneratesRegister()
+                         ? g.ToRegister(destination)
+                         : scope.AcquireX();
       if (src.type() == Constant::kHeapObject) {
         Handle<HeapObject> src_object = src.ToHeapObject();
         Heap::RootListIndex index;
         int offset;
         if (IsMaterializableFromFrame(src_object, &offset)) {
           __ Ldr(dst, MemOperand(fp, offset));
         } else if (IsMaterializableFromRoot(src_object, &index)) {
           __ LoadRoot(dst, index);
         } else {
           __ LoadObject(dst, src_object);
@@ skipping 52 matching lines @@
     UNREACHABLE();
   }
 }
 
 
 void CodeGenerator::AssembleSwap(InstructionOperand* source,
                                  InstructionOperand* destination) {
   Arm64OperandConverter g(this, NULL);
   // Dispatch on the source and destination operand kinds.  Not all
   // combinations are possible.
-  if (source->IsRegister()) {
+  if (source->GeneratesRegister()) {
     // Register-register.
     UseScratchRegisterScope scope(masm());
     Register temp = scope.AcquireX();
     Register src = g.ToRegister(source);
-    if (destination->IsRegister()) {
+    if (destination->GeneratesRegister()) {
       Register dst = g.ToRegister(destination);
       __ Mov(temp, src);
       __ Mov(src, dst);
       __ Mov(dst, temp);
     } else {
       DCHECK(destination->IsStackSlot());
       MemOperand dst = g.ToMemOperand(destination, masm());
       __ Mov(temp, src);
       __ Ldr(src, dst);
       __ Str(temp, dst);
@@ skipping 59 matching lines @@
       }
     }
   }
 }
 
 #undef __
 
 }  // namespace compiler
 }  // namespace internal
 }  // namespace v8