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Issue 1241863002: VM: Refactor allocation stats code and remove duplicate code. (Closed) Base URL: git@github.com:dart-lang/sdk.git@master
Patch Set: addressed comments Created 5 years, 5 months ago
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1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file 1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file
2 // for details. All rights reserved. Use of this source code is governed by a 2 // for details. All rights reserved. Use of this source code is governed by a
3 // BSD-style license that can be found in the LICENSE file. 3 // BSD-style license that can be found in the LICENSE file.
4 4
5 #include "vm/globals.h" // NOLINT 5 #include "vm/globals.h" // NOLINT
6 #if defined(TARGET_ARCH_IA32) 6 #if defined(TARGET_ARCH_IA32)
7 7
8 #include "vm/assembler.h" 8 #include "vm/assembler.h"
9 #include "vm/code_generator.h" 9 #include "vm/code_generator.h"
10 #include "vm/cpu.h" 10 #include "vm/cpu.h"
(...skipping 2642 matching lines...) Expand 10 before | Expand all | Expand 10 after
2653 while (label->HasNear()) { 2653 while (label->HasNear()) {
2654 intptr_t position = label->NearPosition(); 2654 intptr_t position = label->NearPosition();
2655 intptr_t offset = bound - (position + 1); 2655 intptr_t offset = bound - (position + 1);
2656 ASSERT(Utils::IsInt(8, offset)); 2656 ASSERT(Utils::IsInt(8, offset));
2657 buffer_.Store<int8_t>(position, offset); 2657 buffer_.Store<int8_t>(position, offset);
2658 } 2658 }
2659 label->BindTo(bound); 2659 label->BindTo(bound);
2660 } 2660 }
2661 2661
2662 2662
2663 static void ComputeCounterAddressesForCid(intptr_t cid,
2664 Heap::Space space,
2665 Address* count_address,
2666 Address* size_address) {
2667 ASSERT(cid < kNumPredefinedCids);
2668 Isolate* isolate = Isolate::Current();
2669 ClassTable* class_table = isolate->class_table();
2670 const uword class_heap_stats_table_address =
2671 class_table->PredefinedClassHeapStatsTableAddress();
2672 const uword class_offset = cid * sizeof(ClassHeapStats); // NOLINT
2673 const uword count_field_offset = (space == Heap::kNew) ?
2674 ClassHeapStats::allocated_since_gc_new_space_offset() :
2675 ClassHeapStats::allocated_since_gc_old_space_offset();
2676 const uword size_field_offset = (space == Heap::kNew) ?
2677 ClassHeapStats::allocated_size_since_gc_new_space_offset() :
2678 ClassHeapStats::allocated_size_since_gc_old_space_offset();
2679 *count_address = Address::Absolute(
2680 class_heap_stats_table_address + class_offset + count_field_offset);
2681 *size_address = Address::Absolute(
2682 class_heap_stats_table_address + class_offset + size_field_offset);
2683 }
2684
2685
2686 static void ComputeHeapStatsStateAddressForCid(intptr_t cid,
2687 Address* state_address) {
2688 ASSERT(cid < kNumPredefinedCids);
2689 Isolate* isolate = Isolate::Current();
2690 ClassTable* class_table = isolate->class_table();
2691 const uword class_heap_stats_table_address =
2692 class_table->PredefinedClassHeapStatsTableAddress();
2693 const uword class_offset = cid * sizeof(ClassHeapStats); // NOLINT
2694 const uword state_offset = ClassHeapStats::state_offset();
2695 *state_address = Address::Absolute(class_heap_stats_table_address +
2696 class_offset +
2697 state_offset);
2698 }
2699
2700
2701 void Assembler::MaybeTraceAllocation(intptr_t cid, 2663 void Assembler::MaybeTraceAllocation(intptr_t cid,
2702 Register temp_reg, 2664 Register temp_reg,
2703 Label* trace, 2665 Label* trace,
2704 bool near_jump) { 2666 bool near_jump) {
2705 ASSERT(cid > 0); 2667 ASSERT(cid > 0);
2706 Address state_address(kNoRegister, 0); 2668 Address state_address(kNoRegister, 0);
2669 intptr_t state_offset;
2670 ClassTable* class_table = Isolate::Current()->class_table();
2671 ClassHeapStats** table_ptr =
2672 class_table->StateAddressFor(cid, &state_offset);
2707 if (cid < kNumPredefinedCids) { 2673 if (cid < kNumPredefinedCids) {
2708 ComputeHeapStatsStateAddressForCid(cid, &state_address); 2674 state_address = Address::Absolute(
2675 reinterpret_cast<uword>(*table_ptr) + state_offset);
2709 } else { 2676 } else {
2710 ASSERT(temp_reg != kNoRegister); 2677 ASSERT(temp_reg != kNoRegister);
2711 const uword class_offset = cid * sizeof(ClassHeapStats); // NOLINT
2712 const uword state_offset = ClassHeapStats::state_offset();
2713 // temp_reg gets address of class table pointer. 2678 // temp_reg gets address of class table pointer.
2714 ClassTable* class_table = Isolate::Current()->class_table(); 2679 movl(temp_reg,
2715 movl(temp_reg, Address::Absolute(class_table->ClassStatsTableAddress())); 2680 Address::Absolute(reinterpret_cast<uword>(table_ptr)));
2716 state_address = Address(temp_reg, class_offset + state_offset); 2681 state_address = Address(temp_reg, state_offset);
2717 } 2682 }
2718 testb(state_address, Immediate(ClassHeapStats::TraceAllocationMask())); 2683 testb(state_address, Immediate(ClassHeapStats::TraceAllocationMask()));
2719 // We are tracing for this class, jump to the trace label which will use 2684 // We are tracing for this class, jump to the trace label which will use
2720 // the allocation stub. 2685 // the allocation stub.
2721 j(NOT_ZERO, trace, near_jump); 2686 j(NOT_ZERO, trace, near_jump);
2722 } 2687 }
2723 2688
2724 2689
2725 void Assembler::UpdateAllocationStats(intptr_t cid, 2690 void Assembler::UpdateAllocationStats(intptr_t cid,
2726 Register temp_reg, 2691 Register temp_reg,
2727 Heap::Space space) { 2692 Heap::Space space,
2693 bool inline_isolate) {
2728 ASSERT(cid > 0); 2694 ASSERT(cid > 0);
2729 if (cid < kNumPredefinedCids) { 2695 intptr_t counter_offset =
2730 Address count_address(kNoRegister, 0), size_address(kNoRegister, 0); 2696 ClassTable::CounterOffsetFor(cid, space == Heap::kNew);
2731 ComputeCounterAddressesForCid(cid, space, &count_address, &size_address); 2697 if (inline_isolate) {
2732 incl(count_address); 2698 ClassTable* class_table = Isolate::Current()->class_table();
2699 ClassHeapStats** table_ptr = class_table->TableAddressFor(cid);
2700 if (cid < kNumPredefinedCids) {
2701 incl(Address::Absolute(
2702 reinterpret_cast<uword>(*table_ptr) + counter_offset));
2703 } else {
2704 ASSERT(temp_reg != kNoRegister);
2705 movl(temp_reg,
2706 Address::Absolute(reinterpret_cast<uword>(table_ptr)));
2707 incl(Address(temp_reg, counter_offset));
2708 }
2733 } else { 2709 } else {
2734 ASSERT(temp_reg != kNoRegister); 2710 ASSERT(temp_reg != kNoRegister);
2735 const uword class_offset = cid * sizeof(ClassHeapStats); // NOLINT 2711 LoadIsolate(temp_reg);
2736 const uword count_field_offset = (space == Heap::kNew) ? 2712 intptr_t table_offset =
2737 ClassHeapStats::allocated_since_gc_new_space_offset() : 2713 Isolate::class_table_offset() + ClassTable::TableOffsetFor(cid);
2738 ClassHeapStats::allocated_since_gc_old_space_offset(); 2714 movl(temp_reg, Address(temp_reg, table_offset));
2739 // temp_reg gets address of class table pointer. 2715 incl(Address(temp_reg, counter_offset));
2740 ClassTable* class_table = Isolate::Current()->class_table();
2741 movl(temp_reg, Address::Absolute(class_table->ClassStatsTableAddress()));
2742 // Increment allocation count.
2743 incl(Address(temp_reg, class_offset + count_field_offset));
2744 } 2716 }
2745 } 2717 }
2746 2718
2747 2719
2748 void Assembler::UpdateAllocationStatsWithSize(intptr_t cid, 2720 void Assembler::UpdateAllocationStatsWithSize(intptr_t cid,
2749 Register size_reg, 2721 Register size_reg,
2750 Register temp_reg, 2722 Register temp_reg,
2751 Heap::Space space) { 2723 Heap::Space space,
2724 bool inline_isolate) {
2752 ASSERT(cid > 0); 2725 ASSERT(cid > 0);
2753 ASSERT(cid < kNumPredefinedCids); 2726 ASSERT(cid < kNumPredefinedCids);
2754 Address count_address(kNoRegister, 0), size_address(kNoRegister, 0); 2727 UpdateAllocationStats(cid, temp_reg, space, inline_isolate);
2755 ComputeCounterAddressesForCid(cid, space, &count_address, &size_address); 2728 intptr_t size_offset = ClassTable::SizeOffsetFor(cid, space == Heap::kNew);
2756 incl(count_address); 2729 if (inline_isolate) {
2757 addl(size_address, size_reg); 2730 ClassTable* class_table = Isolate::Current()->class_table();
2731 ClassHeapStats** table_ptr = class_table->TableAddressFor(cid);
2732 addl(Address::Absolute(
2733 reinterpret_cast<uword>(*table_ptr) + size_offset), size_reg);
2734 } else {
2735 addl(Address(temp_reg, size_offset), size_reg);
2736 }
2758 } 2737 }
2759 2738
2760 2739
2761 void Assembler::UpdateAllocationStatsWithSize(intptr_t cid, 2740 void Assembler::UpdateAllocationStatsWithSize(intptr_t cid,
2762 intptr_t size_in_bytes, 2741 intptr_t size_in_bytes,
2763 Register temp_reg, 2742 Register temp_reg,
2764 Heap::Space space) { 2743 Heap::Space space,
2744 bool inline_isolate) {
2765 ASSERT(cid > 0); 2745 ASSERT(cid > 0);
2766 ASSERT(cid < kNumPredefinedCids); 2746 ASSERT(cid < kNumPredefinedCids);
2767 Address count_address(kNoRegister, 0), size_address(kNoRegister, 0); 2747 UpdateAllocationStats(cid, temp_reg, space, inline_isolate);
2768 ComputeCounterAddressesForCid(cid, space, &count_address, &size_address); 2748 intptr_t size_offset = ClassTable::SizeOffsetFor(cid, space == Heap::kNew);
2769 incl(count_address); 2749 if (inline_isolate) {
2770 addl(size_address, Immediate(size_in_bytes)); 2750 ClassTable* class_table = Isolate::Current()->class_table();
2751 ClassHeapStats** table_ptr = class_table->TableAddressFor(cid);
2752 addl(Address::Absolute(reinterpret_cast<uword>(*table_ptr) + size_offset),
2753 Immediate(size_in_bytes));
2754 } else {
2755 addl(Address(temp_reg, size_offset), Immediate(size_in_bytes));
2756 }
2771 } 2757 }
2772 2758
2773 2759
2774 void Assembler::TryAllocate(const Class& cls, 2760 void Assembler::TryAllocate(const Class& cls,
2775 Label* failure, 2761 Label* failure,
2776 bool near_jump, 2762 bool near_jump,
2777 Register instance_reg, 2763 Register instance_reg,
2778 Register temp_reg) { 2764 Register temp_reg) {
2779 ASSERT(failure != NULL); 2765 ASSERT(failure != NULL);
2780 if (FLAG_inline_alloc) { 2766 if (FLAG_inline_alloc) {
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3199 3185
3200 const char* Assembler::FpuRegisterName(FpuRegister reg) { 3186 const char* Assembler::FpuRegisterName(FpuRegister reg) {
3201 ASSERT((0 <= reg) && (reg < kNumberOfXmmRegisters)); 3187 ASSERT((0 <= reg) && (reg < kNumberOfXmmRegisters));
3202 return xmm_reg_names[reg]; 3188 return xmm_reg_names[reg];
3203 } 3189 }
3204 3190
3205 3191
3206 } // namespace dart 3192 } // namespace dart
3207 3193
3208 #endif // defined TARGET_ARCH_IA32 3194 #endif // defined TARGET_ARCH_IA32
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