ARM: Add a postRA pass to legalize stack offsets. Greedy approach (reserve IP).

src/IceInstARM32.def

Index: src/IceInstARM32.def
diff --git a/src/IceInstARM32.def b/src/IceInstARM32.def
index 93b1e22a07b000b67b7d628ee036a93c3cc3e953..5bf54ee24054887c1803d28cd0d54c3f8e42835d 100644
--- a/src/IceInstARM32.def
+++ b/src/IceInstARM32.def
@@ -20,6 +20,9 @@
 // TODO(jvoung): Allow r9 to be isInt when sandboxing is turned off
 // (native mode).
 //
+// IP is not considered isInt to reserve it as a scratch register. A scratch
+// register is useful for expanding instructions post-register allocation.
+//
 // LR is not considered isInt to avoid being allocated as a register.
 // It is technically preserved, but save/restore is handled separately,
 // based on whether or not the function MaybeLeafFunc.
@@ -37,7 +40,7 @@
   X(Reg_r9,  = Reg_r0 + 9,   "r9",  0, 1, 0, 0, 0, 0)                   \
   X(Reg_r10, = Reg_r0 + 10,  "r10", 0, 1, 0, 0, 1, 0)                   \
   X(Reg_fp,  = Reg_r0 + 11,  "fp",  0, 1, 0, 1, 1, 0)                   \
-  X(Reg_ip,  = Reg_r0 + 12,  "ip",  1, 0, 0, 0, 1, 0)                   \
+  X(Reg_ip,  = Reg_r0 + 12,  "ip",  1, 0, 0, 0, 0, 0)                   \
   X(Reg_sp,  = Reg_r0 + 13,  "sp",  0, 0, 1, 0, 0, 0)                   \
   X(Reg_lr,  = Reg_r0 + 14,  "lr",  0, 0, 0, 0, 0, 0)                   \
   X(Reg_pc,  = Reg_r0 + 15,  "pc",  0, 0, 0, 0, 0, 0)                   \