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1 //===- subzero/src/IceTargetLoweringX86BaseImpl.h - x86 lowering -*- C++ -*-==// | 1 //===- subzero/src/IceTargetLoweringX86BaseImpl.h - x86 lowering -*- C++ -*-==// |
2 // | 2 // |
3 // The Subzero Code Generator | 3 // The Subzero Code Generator |
4 // | 4 // |
5 // This file is distributed under the University of Illinois Open Source | 5 // This file is distributed under the University of Illinois Open Source |
6 // License. See LICENSE.TXT for details. | 6 // License. See LICENSE.TXT for details. |
7 // | 7 // |
8 //===----------------------------------------------------------------------===// | 8 //===----------------------------------------------------------------------===// |
9 /// | 9 /// |
10 /// \file | 10 /// \file |
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740 return Reg; | 740 return Reg; |
741 } | 741 } |
742 | 742 |
743 template <class Machine> | 743 template <class Machine> |
744 IceString TargetX86Base<Machine>::getRegName(SizeT RegNum, Type Ty) const { | 744 IceString TargetX86Base<Machine>::getRegName(SizeT RegNum, Type Ty) const { |
745 return Traits::getRegName(RegNum, Ty); | 745 return Traits::getRegName(RegNum, Ty); |
746 } | 746 } |
747 | 747 |
748 template <class Machine> | 748 template <class Machine> |
749 void TargetX86Base<Machine>::emitVariable(const Variable *Var) const { | 749 void TargetX86Base<Machine>::emitVariable(const Variable *Var) const { |
| 750 if (!BuildDefs::dump()) |
| 751 return; |
750 Ostream &Str = Ctx->getStrEmit(); | 752 Ostream &Str = Ctx->getStrEmit(); |
751 if (Var->hasReg()) { | 753 if (Var->hasReg()) { |
752 Str << "%" << getRegName(Var->getRegNum(), Var->getType()); | 754 Str << "%" << getRegName(Var->getRegNum(), Var->getType()); |
753 return; | 755 return; |
754 } | 756 } |
755 if (Var->getWeight().isInf()) { | 757 if (Var->getWeight().isInf()) { |
756 llvm_unreachable("Infinite-weight Variable has no register assigned"); | 758 llvm_unreachable("Infinite-weight Variable has no register assigned"); |
757 } | 759 } |
758 int32_t Offset = Var->getStackOffset(); | 760 int32_t Offset = Var->getStackOffset(); |
759 if (!hasFramePointer()) | 761 int32_t BaseRegNum = Var->getBaseRegNum(); |
760 Offset += getStackAdjustment(); | 762 if (BaseRegNum == Variable::NoRegister) { |
| 763 BaseRegNum = getFrameOrStackReg(); |
| 764 if (!hasFramePointer()) |
| 765 Offset += getStackAdjustment(); |
| 766 } |
761 if (Offset) | 767 if (Offset) |
762 Str << Offset; | 768 Str << Offset; |
763 const Type FrameSPTy = IceType_i32; | 769 const Type FrameSPTy = IceType_i32; |
764 Str << "(%" << getRegName(getFrameOrStackReg(), FrameSPTy) << ")"; | 770 Str << "(%" << getRegName(BaseRegNum, FrameSPTy) << ")"; |
765 } | 771 } |
766 | 772 |
767 template <class Machine> | 773 template <class Machine> |
768 typename TargetX86Base<Machine>::Traits::Address | 774 typename TargetX86Base<Machine>::Traits::Address |
769 TargetX86Base<Machine>::stackVarToAsmOperand(const Variable *Var) const { | 775 TargetX86Base<Machine>::stackVarToAsmOperand(const Variable *Var) const { |
770 if (Var->hasReg()) | 776 if (Var->hasReg()) |
771 llvm_unreachable("Stack Variable has a register assigned"); | 777 llvm_unreachable("Stack Variable has a register assigned"); |
772 if (Var->getWeight().isInf()) { | 778 if (Var->getWeight().isInf()) { |
773 llvm_unreachable("Infinite-weight Variable has no register assigned"); | 779 llvm_unreachable("Infinite-weight Variable has no register assigned"); |
774 } | 780 } |
775 int32_t Offset = Var->getStackOffset(); | 781 int32_t Offset = Var->getStackOffset(); |
776 if (!hasFramePointer()) | 782 int32_t BaseRegNum = Var->getBaseRegNum(); |
777 Offset += getStackAdjustment(); | 783 if (Var->getBaseRegNum() == Variable::NoRegister) { |
| 784 BaseRegNum = getFrameOrStackReg(); |
| 785 if (!hasFramePointer()) |
| 786 Offset += getStackAdjustment(); |
| 787 } |
778 return typename Traits::Address( | 788 return typename Traits::Address( |
779 Traits::RegisterSet::getEncodedGPR(getFrameOrStackReg()), Offset); | 789 Traits::RegisterSet::getEncodedGPR(BaseRegNum), Offset); |
780 } | 790 } |
781 | 791 |
782 template <class Machine> void TargetX86Base<Machine>::lowerArguments() { | 792 template <class Machine> void TargetX86Base<Machine>::lowerArguments() { |
783 VarList &Args = Func->getArgs(); | 793 VarList &Args = Func->getArgs(); |
784 // The first four arguments of vector type, regardless of their | 794 // The first four arguments of vector type, regardless of their |
785 // position relative to the other arguments in the argument list, are | 795 // position relative to the other arguments in the argument list, are |
786 // passed in registers xmm0 - xmm3. | 796 // passed in registers xmm0 - xmm3. |
787 unsigned NumXmmArgs = 0; | 797 unsigned NumXmmArgs = 0; |
788 | 798 |
789 Context.init(Func->getEntryNode()); | 799 Context.init(Func->getEntryNode()); |
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5616 } | 5626 } |
5617 // the offset is not eligible for blinding or pooling, return the original | 5627 // the offset is not eligible for blinding or pooling, return the original |
5618 // mem operand | 5628 // mem operand |
5619 return MemOperand; | 5629 return MemOperand; |
5620 } | 5630 } |
5621 | 5631 |
5622 } // end of namespace X86Internal | 5632 } // end of namespace X86Internal |
5623 } // end of namespace Ice | 5633 } // end of namespace Ice |
5624 | 5634 |
5625 #endif // SUBZERO_SRC_ICETARGETLOWERINGX86BASEIMPL_H | 5635 #endif // SUBZERO_SRC_ICETARGETLOWERINGX86BASEIMPL_H |
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