ARM: Add a postRA pass to legalize stack offsets. Greedy approach (reserve IP).

src/IceTargetLoweringARM32.h

 //===- subzero/src/IceTargetLoweringARM32.h - ARM32 lowering ----*- C++ -*-===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 54 matching lines @@
   IceString getRegName(SizeT RegNum, Type Ty) const override;
   llvm::SmallBitVector getRegisterSet(RegSetMask Include,
                                       RegSetMask Exclude) const override;
   const llvm::SmallBitVector &getRegisterSetForType(Type Ty) const override {
     return TypeToRegisterSet[Ty];
   }
   bool hasFramePointer() const override { return UsesFramePointer; }
   SizeT getFrameOrStackReg() const override {
     return UsesFramePointer ? RegARM32::Reg_fp : RegARM32::Reg_sp;
   }
+  SizeT getReservedTmpReg() const { return RegARM32::Reg_ip; }
+
   size_t typeWidthInBytesOnStack(Type Ty) const override {
     // Round up to the next multiple of 4 bytes.  In particular, i1,
     // i8, and i16 are rounded up to 4 bytes.
     return (typeWidthInBytes(Ty) + 3) & ~3;
   }
 
   // TODO(ascull): what size is best for ARM?
   SizeT getMinJumpTableSize() const override { return 3; }
 
   void emitVariable(const Variable *Var) const override;
@@ skipping 288 matching lines @@
         InstARM32Umull::create(Func, DestLo, DestHi, Src0, Src1, Pred));
     // Model the modification to the second dest as a fake def.
     // Note that the def is not predicated.
     Context.insert(InstFakeDef::create(Func, DestHi, DestLo));
   }
   void _uxt(Variable *Dest, Variable *Src0,
             CondARM32::Cond Pred = CondARM32::AL) {
     Context.insert(InstARM32Uxt::create(Func, Dest, Src0, Pred));
   }
 
+  /// Run a pass through stack variables and ensure that the offsets are legal.
+  /// If the offset is not legal, use a new base register that accounts for
+  /// the offset, such that the addressing mode offset bits are now legal.
+  void legalizeStackSlots();
+  /// Returns true if the given Offset can be represented in a stack ldr/str.
+  bool isLegalVariableStackOffset(int32_t Offset) const;
+  /// Assuming Var needs its offset legalized, define a new base register
+  /// centered on the given Var's offset and use it.
+  StackVariable *legalizeVariableSlot(Variable *Var, Variable *OrigBaseReg);
+
   TargetARM32Features CPUFeatures;
   bool UsesFramePointer = false;
   bool NeedsStackAlignment = false;
   bool MaybeLeafFunc = true;
   size_t SpillAreaSizeBytes = 0;
   llvm::SmallBitVector TypeToRegisterSet[IceType_NUM];
   llvm::SmallBitVector ScratchRegs;
   llvm::SmallBitVector RegsUsed;
   VarList PhysicalRegisters[IceType_NUM];
 
@@ skipping 67 matching lines @@
 
 private:
   ~TargetHeaderARM32() = default;
 
   TargetARM32Features CPUFeatures;
 };
 
 } // end of namespace Ice
 
 #endif // SUBZERO_SRC_ICETARGETLOWERINGARM32_H