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1 //===- subzero/src/IceInstARM32.cpp - ARM32 instruction implementation ----===// | 1 //===- subzero/src/IceInstARM32.cpp - ARM32 instruction implementation ----===// |
2 // | 2 // |
3 // The Subzero Code Generator | 3 // The Subzero Code Generator |
4 // | 4 // |
5 // This file is distributed under the University of Illinois Open Source | 5 // This file is distributed under the University of Illinois Open Source |
6 // License. See LICENSE.TXT for details. | 6 // License. See LICENSE.TXT for details. |
7 // | 7 // |
8 //===----------------------------------------------------------------------===// | 8 //===----------------------------------------------------------------------===// |
9 /// | 9 /// |
10 /// \file | 10 /// \file |
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400 if (!BuildDefs::dump()) | 400 if (!BuildDefs::dump()) |
401 return; | 401 return; |
402 Ostream &Str = Func->getContext()->getStrEmit(); | 402 Ostream &Str = Func->getContext()->getStrEmit(); |
403 assert(getSrcSize() == 1); | 403 assert(getSrcSize() == 1); |
404 Variable *Dest = getDest(); | 404 Variable *Dest = getDest(); |
405 if (Dest->hasReg()) { | 405 if (Dest->hasReg()) { |
406 IceString Opcode = "mov"; | 406 IceString Opcode = "mov"; |
407 Operand *Src0 = getSrc(0); | 407 Operand *Src0 = getSrc(0); |
408 if (const auto *Src0V = llvm::dyn_cast<Variable>(Src0)) { | 408 if (const auto *Src0V = llvm::dyn_cast<Variable>(Src0)) { |
409 if (!Src0V->hasReg()) { | 409 if (!Src0V->hasReg()) { |
410 Opcode = IceString("ldr"); // Always use the whole stack slot. | 410 // Always use the whole stack slot. A 32-bit load has a larger range |
| 411 // of offsets than 16-bit, etc. |
| 412 Opcode = IceString("ldr"); |
411 } | 413 } |
412 } else { | 414 } else { |
413 if (llvm::isa<OperandARM32Mem>(Src0)) | 415 if (llvm::isa<OperandARM32Mem>(Src0)) |
414 Opcode = IceString("ldr") + getWidthString(Dest->getType()); | 416 Opcode = IceString("ldr") + getWidthString(Dest->getType()); |
415 } | 417 } |
416 Str << "\t" << Opcode << getPredicate() << "\t"; | 418 Str << "\t" << Opcode << getPredicate() << "\t"; |
417 getDest()->emit(Func); | 419 getDest()->emit(Func); |
418 Str << ", "; | 420 Str << ", "; |
419 getSrc(0)->emit(Func); | 421 getSrc(0)->emit(Func); |
420 } else { | 422 } else { |
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933 if (getShiftOp() != kNoShift) { | 935 if (getShiftOp() != kNoShift) { |
934 Str << ", " << InstARM32ShiftAttributes[getShiftOp()].EmitString << " "; | 936 Str << ", " << InstARM32ShiftAttributes[getShiftOp()].EmitString << " "; |
935 if (Func) | 937 if (Func) |
936 getShiftAmt()->dump(Func); | 938 getShiftAmt()->dump(Func); |
937 else | 939 else |
938 getShiftAmt()->dump(Str); | 940 getShiftAmt()->dump(Str); |
939 } | 941 } |
940 } | 942 } |
941 | 943 |
942 } // end of namespace Ice | 944 } // end of namespace Ice |
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