ARM: Add a postRA pass to legalize stack offsets. Greedy approach (reserve IP).

src/IceInstARM32.h

 //===- subzero/src/IceInstARM32.h - ARM32 machine instructions --*- C++ -*-===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 224 matching lines @@
 
 private:
   OperandARM32FlexReg(Cfg *Func, Type Ty, Variable *Reg, ShiftKind ShiftOp,
                       Operand *ShiftAmt);
 
   Variable *Reg;
   ShiftKind ShiftOp;
   Operand *ShiftAmt;
 };
 
+/// StackVariable represents a Var that isn't assigned a register (stack-only).
+/// It is assigned a stack slot, but the slot's offset may be too large to
+/// represent in the native addressing mode, and so it has a separate
+/// base register from SP/FP, where the offset from that base register is
+/// then in range.
+class StackVariable final : public Variable {
+  StackVariable() = delete;
+  StackVariable(const StackVariable &) = delete;
+  StackVariable &operator=(const StackVariable &) = delete;
+
+public:
+  static StackVariable *create(Cfg *Func, Type Ty, SizeT Index) {
+    return new (Func->allocate<StackVariable>()) StackVariable(Ty, Index);
+  }
+  const static OperandKind StackVariableKind =
+      static_cast<OperandKind>(kVariable_Target);
+  static bool classof(const Operand *Operand) {
+    return Operand->getKind() == StackVariableKind;
+  }
+  void setBaseRegNum(int32_t RegNum) { BaseRegNum = RegNum; }
+  int32_t getBaseRegNum() const override { return BaseRegNum; }
+  // Inherit dump() and emit() from Variable.
+
+private:
+  StackVariable(Type Ty, SizeT Index)
+      : Variable(StackVariableKind, Ty, Index),
+        BaseRegNum(Variable::NoRegister) {}
+  int32_t BaseRegNum;

[Jim Stichnoth, 2015/07/24 22:08:29]

int32_t BaseRegNum = Variable::NoRegister;

Then you can drop it from the initialization list.

[jvoung (off chromium), 2015/07/27 17:02:57]

Done.

+};
+
 /// Base class for ARM instructions. While most ARM instructions can be
 /// conditionally executed, a few of them are not predicable (halt,
 /// memory barriers, etc.).
 class InstARM32 : public InstTarget {
   InstARM32() = delete;
   InstARM32(const InstARM32 &) = delete;
   InstARM32 &operator=(const InstARM32 &) = delete;
 
 public:
   enum InstKindARM32 {
@@ skipping 516 matching lines @@
   /// hard to pull that from the generic SrcAmount operand.
   static InstARM32AdjustStack *create(Cfg *Func, Variable *SP, SizeT Amount,
                                       Operand *SrcAmount) {
     return new (Func->allocate<InstARM32AdjustStack>())
         InstARM32AdjustStack(Func, SP, Amount, SrcAmount);
   }
   void emit(const Cfg *Func) const override;
   void emitIAS(const Cfg *Func) const override;
   void dump(const Cfg *Func) const override;
   static bool classof(const Inst *Inst) { return isClassof(Inst, Adjuststack); }
+  SizeT getAmount() const { return Amount; }
 
 private:
   InstARM32AdjustStack(Cfg *Func, Variable *SP, SizeT Amount,
                        Operand *SrcAmount);
   const SizeT Amount;
 };
 
 /// Call instruction (bl/blx).  Arguments should have already been pushed.
 /// Technically bl and the register form of blx can be predicated, but we'll
 /// leave that out until needed.
@@ skipping 181 matching lines @@
 // Declare partial template specializations of emit() methods that
 // already have default implementations.  Without this, there is the
 // possibility of ODR violations and link errors.
 
 template <> void InstARM32Movw::emit(const Cfg *Func) const;
 template <> void InstARM32Movt::emit(const Cfg *Func) const;
 
 } // end of namespace Ice
 
 #endif // SUBZERO_SRC_ICEINSTARM32_H