Cleaned up CpuFeature scope handling.

src/mips/code-stubs-mips.cc

 // Copyright 2012 the V8 project authors. All rights reserved.
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions are
 // met:
 //
 //     * Redistributions of source code must retain the above copyright
 //       notice, this list of conditions and the following disclaimer.
 //     * Redistributions in binary form must reproduce the above
 //       copyright notice, this list of conditions and the following
 //       disclaimer in the documentation and/or other materials provided
@@ skipping 627 matching lines @@
   __ Ret(USE_DELAY_SLOT);
   __ or_(exponent, exponent, source_);
 }
 
 
 void FloatingPointHelper::LoadSmis(MacroAssembler* masm,
                                    FloatingPointHelper::Destination destination,
                                    Register scratch1,
                                    Register scratch2) {
   if (CpuFeatures::IsSupported(FPU)) {
-    CpuFeatures::Scope scope(FPU);
+    CpuFeatureScope scope(masm, FPU);
     __ sra(scratch1, a0, kSmiTagSize);
     __ mtc1(scratch1, f14);
     __ cvt_d_w(f14, f14);
     __ sra(scratch1, a1, kSmiTagSize);
     __ mtc1(scratch1, f12);
     __ cvt_d_w(f12, f12);
     if (destination == kCoreRegisters) {
       __ Move(a2, a3, f14);
       __ Move(a0, a1, f12);
     }
@@ skipping 30 matching lines @@
   Label is_smi, done;
 
   // Smi-check
   __ UntagAndJumpIfSmi(scratch1, object, &is_smi);
   // Heap number check
   __ JumpIfNotHeapNumber(object, heap_number_map, scratch1, not_number);
 
   // Handle loading a double from a heap number.
   if (CpuFeatures::IsSupported(FPU) &&
       destination == kFPURegisters) {
-    CpuFeatures::Scope scope(FPU);
+    CpuFeatureScope scope(masm, FPU);
     // Load the double from tagged HeapNumber to double register.
 
     // ARM uses a workaround here because of the unaligned HeapNumber
     // kValueOffset. On MIPS this workaround is built into ldc1 so there's no
     // point in generating even more instructions.
     __ ldc1(dst, FieldMemOperand(object, HeapNumber::kValueOffset));
   } else {
     ASSERT(destination == kCoreRegisters);
     // Load the double from heap number to dst1 and dst2 in double format.
     __ lw(dst1, FieldMemOperand(object, HeapNumber::kValueOffset));
     __ lw(dst2, FieldMemOperand(object,
         HeapNumber::kValueOffset + kPointerSize));
   }
   __ Branch(&done);
 
   // Handle loading a double from a smi.
   __ bind(&is_smi);
   if (CpuFeatures::IsSupported(FPU)) {
-    CpuFeatures::Scope scope(FPU);
+    CpuFeatureScope scope(masm, FPU);
     // Convert smi to double using FPU instructions.
     __ mtc1(scratch1, dst);
     __ cvt_d_w(dst, dst);
     if (destination == kCoreRegisters) {
       // Load the converted smi to dst1 and dst2 in double format.
       __ Move(dst1, dst2, dst);
     }
   } else {
     ASSERT(destination == kCoreRegisters);
     // Write smi to dst1 and dst2 double format.
@@ skipping 55 matching lines @@
                                              Register dst_exponent,
                                              Register scratch2,
                                              FPURegister single_scratch) {
   ASSERT(!int_scratch.is(scratch2));
   ASSERT(!int_scratch.is(dst_mantissa));
   ASSERT(!int_scratch.is(dst_exponent));
 
   Label done;
 
   if (CpuFeatures::IsSupported(FPU)) {
-    CpuFeatures::Scope scope(FPU);
+    CpuFeatureScope scope(masm, FPU);
     __ mtc1(int_scratch, single_scratch);
     __ cvt_d_w(double_dst, single_scratch);
     if (destination == kCoreRegisters) {
       __ Move(dst_mantissa, dst_exponent, double_dst);
     }
   } else {
     Label fewer_than_20_useful_bits;
     // Expected output:
     // |       dst_exponent      |       dst_mantissa      |
     // | s |   exp   |              mantissa               |
@@ skipping 81 matching lines @@
   __ Branch(&done);
 
   __ bind(&obj_is_not_smi);
   __ AssertRootValue(heap_number_map,
                      Heap::kHeapNumberMapRootIndex,
                      "HeapNumberMap register clobbered.");
   __ JumpIfNotHeapNumber(object, heap_number_map, scratch1, not_int32);
 
   // Load the number.
   if (CpuFeatures::IsSupported(FPU)) {
-    CpuFeatures::Scope scope(FPU);
+    CpuFeatureScope scope(masm, FPU);
     // Load the double value.
     __ ldc1(double_dst, FieldMemOperand(object, HeapNumber::kValueOffset));
 
     Register except_flag = scratch2;
     __ EmitFPUTruncate(kRoundToZero,
                        scratch1,
                        double_dst,
                        at,
                        double_scratch,
                        except_flag,
@@ skipping 76 matching lines @@
 
   __ AssertRootValue(heap_number_map,
                      Heap::kHeapNumberMapRootIndex,
                      "HeapNumberMap register clobbered.");
 
   __ JumpIfNotHeapNumber(object, heap_number_map, scratch1, &maybe_undefined);
 
   // Object is a heap number.
   // Convert the floating point value to a 32-bit integer.
   if (CpuFeatures::IsSupported(FPU)) {
-    CpuFeatures::Scope scope(FPU);
+    CpuFeatureScope scope(masm, FPU);
     // Load the double value.
     __ ldc1(double_scratch0, FieldMemOperand(object, HeapNumber::kValueOffset));
 
     Register except_flag = scratch2;
     __ EmitFPUTruncate(kRoundToZero,
                        dst,
                        double_scratch0,
                        scratch1,
                        double_scratch1,
                        except_flag,
@@ skipping 117 matching lines @@
   // a3: Right value (sign, exponent, top of mantissa).
 
   // Assert that heap_number_result is saved.
   // We currently always use s0 to pass it.
   ASSERT(heap_number_result.is(s0));
 
   // Push the current return address before the C call.
   __ push(ra);
   __ PrepareCallCFunction(4, scratch);  // Two doubles are 4 arguments.
   if (!IsMipsSoftFloatABI) {
-    CpuFeatures::Scope scope(FPU);
+    CpuFeatureScope scope(masm, FPU);
     // We are not using MIPS FPU instructions, and parameters for the runtime
     // function call are prepaired in a0-a3 registers, but function we are
     // calling is compiled with hard-float flag and expecting hard float ABI
     // (parameters in f12/f14 registers). We need to copy parameters from
     // a0-a3 registers to f12/f14 register pairs.
     __ Move(f12, a0, a1);
     __ Move(f14, a2, a3);
   }
   {
     AllowExternalCallThatCantCauseGC scope(masm);
     __ CallCFunction(
         ExternalReference::double_fp_operation(op, masm->isolate()), 0, 2);
   }
   // Store answer in the overwritable heap number.
   if (!IsMipsSoftFloatABI) {
-    CpuFeatures::Scope scope(FPU);
+    CpuFeatureScope scope(masm, FPU);
     // Double returned in register f0.
     __ sdc1(f0, FieldMemOperand(heap_number_result, HeapNumber::kValueOffset));
   } else {
     // Double returned in registers v0 and v1.
     __ sw(v1, FieldMemOperand(heap_number_result, HeapNumber::kExponentOffset));
     __ sw(v0, FieldMemOperand(heap_number_result, HeapNumber::kMantissaOffset));
   }
   // Place heap_number_result in v0 and return to the pushed return address.
   __ pop(ra);
   __ Ret(USE_DELAY_SLOT);
@@ skipping 203 matching lines @@
     __ mov(v0, lhs);
   } else {
     // Smi compared non-strictly with a non-Smi non-heap-number. Call
     // the runtime.
     __ Branch(slow, ne, t4, Operand(HEAP_NUMBER_TYPE));
   }
 
   // Rhs is a smi, lhs is a number.
   // Convert smi rhs to double.
   if (CpuFeatures::IsSupported(FPU)) {
-    CpuFeatures::Scope scope(FPU);
+    CpuFeatureScope scope(masm, FPU);
     __ sra(at, rhs, kSmiTagSize);
     __ mtc1(at, f14);
     __ cvt_d_w(f14, f14);
     __ ldc1(f12, FieldMemOperand(lhs, HeapNumber::kValueOffset));
   } else {
     // Load lhs to a double in a2, a3.
     __ lw(a3, FieldMemOperand(lhs, HeapNumber::kValueOffset + 4));
     __ lw(a2, FieldMemOperand(lhs, HeapNumber::kValueOffset));
 
     // Write Smi from rhs to a1 and a0 in double format. t5 is scratch.
@@ skipping 18 matching lines @@
     __ li(v0, Operand(1));
   } else {
     // Smi compared non-strictly with a non-Smi non-heap-number. Call
     // the runtime.
     __ Branch(slow, ne, t4, Operand(HEAP_NUMBER_TYPE));
   }
 
   // Lhs is a smi, rhs is a number.
   // Convert smi lhs to double.
   if (CpuFeatures::IsSupported(FPU)) {
-    CpuFeatures::Scope scope(FPU);
+    CpuFeatureScope scope(masm, FPU);
     __ sra(at, lhs, kSmiTagSize);
     __ mtc1(at, f12);
     __ cvt_d_w(f12, f12);
     __ ldc1(f14, FieldMemOperand(rhs, HeapNumber::kValueOffset));
   } else {
     // Convert lhs to a double format. t5 is scratch.
     __ mov(t6, lhs);
     ConvertToDoubleStub stub2(a3, a2, t6, t5);
     __ push(ra);
     __ Call(stub2.GetCode(masm->isolate()));
     __ pop(ra);
     // Load rhs to a double in a1, a0.
     if (rhs.is(a0)) {
       __ lw(a1, FieldMemOperand(rhs, HeapNumber::kValueOffset + 4));
       __ lw(a0, FieldMemOperand(rhs, HeapNumber::kValueOffset));
     } else {
       __ lw(a0, FieldMemOperand(rhs, HeapNumber::kValueOffset));
       __ lw(a1, FieldMemOperand(rhs, HeapNumber::kValueOffset + 4));
     }
   }
   // Fall through to both_loaded_as_doubles.
 }
 
 
 void EmitNanCheck(MacroAssembler* masm, Condition cc) {
   bool exp_first = (HeapNumber::kExponentOffset == HeapNumber::kValueOffset);
   if (CpuFeatures::IsSupported(FPU)) {
-    CpuFeatures::Scope scope(FPU);
+    CpuFeatureScope scope(masm, FPU);
     // Lhs and rhs are already loaded to f12 and f14 register pairs.
     __ Move(t0, t1, f14);
     __ Move(t2, t3, f12);
   } else {
     // Lhs and rhs are already loaded to GP registers.
     __ mov(t0, a0);  // a0 has LS 32 bits of rhs.
     __ mov(t1, a1);  // a1 has MS 32 bits of rhs.
     __ mov(t2, a2);  // a2 has LS 32 bits of lhs.
     __ mov(t3, a3);  // a3 has MS 32 bits of lhs.
   }
@@ skipping 46 matching lines @@
   // Call C routine that may not cause GC or other trouble.
   // We use a call_was and return manually because we need arguments slots to
   // be freed.
 
   Label return_result_not_equal, return_result_equal;
   if (cc == eq) {
     // Doubles are not equal unless they have the same bit pattern.
     // Exception: 0 and -0.
     bool exp_first = (HeapNumber::kExponentOffset == HeapNumber::kValueOffset);
     if (CpuFeatures::IsSupported(FPU)) {
-      CpuFeatures::Scope scope(FPU);
+      CpuFeatureScope scope(masm, FPU);
       // Lhs and rhs are already loaded to f12 and f14 register pairs.
       __ Move(t0, t1, f14);
       __ Move(t2, t3, f12);
     } else {
       // Lhs and rhs are already loaded to GP registers.
       __ mov(t0, a0);  // a0 has LS 32 bits of rhs.
       __ mov(t1, a1);  // a1 has MS 32 bits of rhs.
       __ mov(t2, a2);  // a2 has LS 32 bits of lhs.
       __ mov(t3, a3);  // a3 has MS 32 bits of lhs.
     }
@@ skipping 35 matching lines @@
       __ Move(f12, a0, a1);
       __ Move(f14, a2, a3);
     }
 
     AllowExternalCallThatCantCauseGC scope(masm);
     __ CallCFunction(ExternalReference::compare_doubles(masm->isolate()),
        0, 2);
     __ pop(ra);  // Because this function returns int, result is in v0.
     __ Ret();
   } else {
-    CpuFeatures::Scope scope(FPU);
+    CpuFeatureScope scope(masm, FPU);
     Label equal, less_than;
     __ BranchF(&equal, NULL, eq, f12, f14);
     __ BranchF(&less_than, NULL, lt, f12, f14);
 
     // Not equal, not less, not NaN, must be greater.
 
     __ li(v0, Operand(GREATER));
     __ Ret();
 
     __ bind(&equal);
@@ skipping 54 matching lines @@
                                        Label* slow) {
   __ GetObjectType(lhs, a3, a2);
   __ Branch(not_heap_numbers, ne, a2, Operand(HEAP_NUMBER_TYPE));
   __ lw(a2, FieldMemOperand(rhs, HeapObject::kMapOffset));
   // If first was a heap number & second wasn't, go to slow case.
   __ Branch(slow, ne, a3, Operand(a2));
 
   // Both are heap numbers. Load them up then jump to the code we have
   // for that.
   if (CpuFeatures::IsSupported(FPU)) {
-    CpuFeatures::Scope scope(FPU);
+    CpuFeatureScope scope(masm, FPU);
     __ ldc1(f12, FieldMemOperand(lhs, HeapNumber::kValueOffset));
     __ ldc1(f14, FieldMemOperand(rhs, HeapNumber::kValueOffset));
   } else {
     __ lw(a2, FieldMemOperand(lhs, HeapNumber::kValueOffset));
     __ lw(a3, FieldMemOperand(lhs, HeapNumber::kValueOffset + 4));
     if (rhs.is(a0)) {
       __ lw(a1, FieldMemOperand(rhs, HeapNumber::kValueOffset + 4));
       __ lw(a0, FieldMemOperand(rhs, HeapNumber::kValueOffset));
     } else {
       __ lw(a0, FieldMemOperand(rhs, HeapNumber::kValueOffset));
@@ skipping 74 matching lines @@
   // Calculate the entry in the number string cache. The hash value in the
   // number string cache for smis is just the smi value, and the hash for
   // doubles is the xor of the upper and lower words. See
   // Heap::GetNumberStringCache.
   Isolate* isolate = masm->isolate();
   Label is_smi;
   Label load_result_from_cache;
   if (!object_is_smi) {
     __ JumpIfSmi(object, &is_smi);
     if (CpuFeatures::IsSupported(FPU)) {
-      CpuFeatures::Scope scope(FPU);
+      CpuFeatureScope scope(masm, FPU);
       __ CheckMap(object,
                   scratch1,
                   Heap::kHeapNumberMapRootIndex,
                   not_found,
                   DONT_DO_SMI_CHECK);
 
       STATIC_ASSERT(8 == kDoubleSize);
       __ Addu(scratch1,
               object,
               Operand(HeapNumber::kValueOffset - kHeapObjectTag));
@@ skipping 132 matching lines @@
   EmitSmiNonsmiComparison(masm, lhs, rhs,
                           &both_loaded_as_doubles, &slow, strict());
 
   __ bind(&both_loaded_as_doubles);
   // f12, f14 are the double representations of the left hand side
   // and the right hand side if we have FPU. Otherwise a2, a3 represent
   // left hand side and a0, a1 represent right hand side.
 
   Isolate* isolate = masm->isolate();
   if (CpuFeatures::IsSupported(FPU)) {
-    CpuFeatures::Scope scope(FPU);
+    CpuFeatureScope scope(masm, FPU);
     Label nan;
     __ li(t0, Operand(LESS));
     __ li(t1, Operand(GREATER));
     __ li(t2, Operand(EQUAL));
 
     // Check if either rhs or lhs is NaN.
     __ BranchF(NULL, &nan, eq, f12, f14);
 
     // Check if LESS condition is satisfied. If true, move conditionally
     // result to v0.
@@ skipping 111 matching lines @@
 
   __ bind(&miss);
   GenerateMiss(masm);
 }
 
 
 // The stub expects its argument in the tos_ register and returns its result in
 // it, too: zero for false, and a non-zero value for true.
 void ToBooleanStub::Generate(MacroAssembler* masm) {
   // This stub uses FPU instructions.
-  CpuFeatures::Scope scope(FPU);
+  CpuFeatureScope scope(masm, FPU);
 
   Label patch;
   const Register map = t5.is(tos_) ? t3 : t5;
 
   // undefined -> false.
   CheckOddball(masm, UNDEFINED, Heap::kUndefinedValueRootIndex, false);
 
   // Boolean -> its value.
   CheckOddball(masm, BOOLEAN, Heap::kFalseValueRootIndex, false);
   CheckOddball(masm, BOOLEAN, Heap::kTrueValueRootIndex, true);
@@ skipping 94 matching lines @@
       1);
 }
 
 
 void StoreBufferOverflowStub::Generate(MacroAssembler* masm) {
   // We don't allow a GC during a store buffer overflow so there is no need to
   // store the registers in any particular way, but we do have to store and
   // restore them.
   __ MultiPush(kJSCallerSaved | ra.bit());
   if (save_doubles_ == kSaveFPRegs) {
-    CpuFeatures::Scope scope(FPU);
+    CpuFeatureScope scope(masm, FPU);
     __ MultiPushFPU(kCallerSavedFPU);
   }
   const int argument_count = 1;
   const int fp_argument_count = 0;
   const Register scratch = a1;
 
   AllowExternalCallThatCantCauseGC scope(masm);
   __ PrepareCallCFunction(argument_count, fp_argument_count, scratch);
   __ li(a0, Operand(ExternalReference::isolate_address()));
   __ CallCFunction(
       ExternalReference::store_buffer_overflow_function(masm->isolate()),
       argument_count);
   if (save_doubles_ == kSaveFPRegs) {
-    CpuFeatures::Scope scope(FPU);
+    CpuFeatureScope scope(masm, FPU);
     __ MultiPopFPU(kCallerSavedFPU);
   }
 
   __ MultiPop(kJSCallerSaved | ra.bit());
   __ Ret();
 }
 
 
 void UnaryOpStub::PrintName(StringStream* stream) {
   const char* op_name = Token::Name(op_);
@@ skipping 212 matching lines @@
     __ ConvertToInt32(v0, a1, a3, t0, f0, &impossible);
     // Negate the result.
     __ Xor(a1, a1, -1);
 
     __ bind(&heapnumber_allocated);
     __ mov(v0, a2);  // Move newly allocated heap number to v0.
   }
 
   if (CpuFeatures::IsSupported(FPU)) {
     // Convert the int32 in a1 to the heap number in v0. a2 is corrupted.
-    CpuFeatures::Scope scope(FPU);
+    CpuFeatureScope scope(masm, FPU);
     __ mtc1(a1, f0);
     __ cvt_d_w(f0, f0);
     __ sdc1(f0, FieldMemOperand(v0, HeapNumber::kValueOffset));
     __ Ret();
   } else {
     // WriteInt32ToHeapNumberStub does not trigger GC, so we do not
     // have to set up a frame.
     WriteInt32ToHeapNumberStub stub(a1, v0, a2, a3);
     __ Jump(stub.GetCode(masm->isolate()), RelocInfo::CODE_TARGET);
   }
@@ skipping 326 matching lines @@
               masm, destination, left, f12, a0, a1, heap_number_map,
               scratch1, scratch2, fail);
         }
       }
 
       // Calculate the result.
       if (destination == FloatingPointHelper::kFPURegisters) {
         // Using FPU registers:
         // f12: Left value.
         // f14: Right value.
-        CpuFeatures::Scope scope(FPU);
+        CpuFeatureScope scope(masm, FPU);
         switch (op) {
         case Token::ADD:
           __ add_d(f10, f12, f14);
           break;
         case Token::SUB:
           __ sub_d(f10, f12, f14);
           break;
         case Token::MUL:
           __ mul_d(f10, f12, f14);
           break;
@@ skipping 111 matching lines @@
       // a2: Answer as signed int32.
       // t1: Heap number to write answer into.
 
       // Nothing can go wrong now, so move the heap number to v0, which is the
       // result.
       __ mov(v0, t1);
 
       if (CpuFeatures::IsSupported(FPU)) {
         // Convert the int32 in a2 to the heap number in a0. As
         // mentioned above SHR needs to always produce a positive result.
-        CpuFeatures::Scope scope(FPU);
+        CpuFeatureScope scope(masm, FPU);
         __ mtc1(a2, f0);
         if (op == Token::SHR) {
           __ Cvt_d_uw(f0, f0, f22);
         } else {
           __ cvt_d_w(f0, f0);
         }
         // ARM uses a workaround here because of the unaligned HeapNumber
         // kValueOffset. On MIPS this workaround is built into sdc1 so
         // there's no point in generating even more instructions.
         __ sdc1(f0, FieldMemOperand(v0, HeapNumber::kValueOffset));
@@ skipping 174 matching lines @@
                                                    f16,
                                                    t0,
                                                    t1,
                                                    heap_number_map,
                                                    scratch1,
                                                    scratch2,
                                                    f2,
                                                    &transition);
 
       if (destination == FloatingPointHelper::kFPURegisters) {
-        CpuFeatures::Scope scope(FPU);
+        CpuFeatureScope scope(masm, FPU);
         Label return_heap_number;
         switch (op_) {
           case Token::ADD:
             __ add_d(f10, f12, f14);
             break;
           case Token::SUB:
             __ sub_d(f10, f12, f14);
             break;
           case Token::MUL:
             __ mul_d(f10, f12, f14);
@@ skipping 193 matching lines @@
       heap_number_result = t1;
       BinaryOpStub_GenerateHeapResultAllocation(masm,
                                                 heap_number_result,
                                                 heap_number_map,
                                                 scratch1,
                                                 scratch2,
                                                 &call_runtime,
                                                 mode_);
 
       if (CpuFeatures::IsSupported(FPU)) {
-        CpuFeatures::Scope scope(FPU);
+        CpuFeatureScope scope(masm, FPU);
 
         if (op_ != Token::SHR) {
           // Convert the result to a floating point value.
           __ mtc1(a2, double_scratch);
           __ cvt_d_w(double_scratch, double_scratch);
         } else {
           // The result must be interpreted as an unsigned 32-bit integer.
           __ mtc1(a2, double_scratch);
           __ Cvt_d_uw(double_scratch, double_scratch, single_scratch);
         }
@@ skipping 183 matching lines @@
   Label input_not_smi;
   Label loaded;
   Label calculate;
   Label invalid_cache;
   const Register scratch0 = t5;
   const Register scratch1 = t3;
   const Register cache_entry = a0;
   const bool tagged = (argument_type_ == TAGGED);
 
   if (CpuFeatures::IsSupported(FPU)) {
-    CpuFeatures::Scope scope(FPU);
+    CpuFeatureScope scope(masm, FPU);
 
     if (tagged) {
       // Argument is a number and is on stack and in a0.
       // Load argument and check if it is a smi.
       __ JumpIfNotSmi(a0, &input_not_smi);
 
       // Input is a smi. Convert to double and load the low and high words
       // of the double into a2, a3.
       __ sra(t0, a0, kSmiTagSize);
       __ mtc1(t0, f4);
@@ skipping 89 matching lines @@
   __ IncrementCounter(
       counters->transcendental_cache_miss(), 1, scratch0, scratch1);
   if (tagged) {
     __ bind(&invalid_cache);
     __ TailCallExternalReference(ExternalReference(RuntimeFunction(),
                                                    masm->isolate()),
                                  1,
                                  1);
   } else {
     ASSERT(CpuFeatures::IsSupported(FPU));
-    CpuFeatures::Scope scope(FPU);
+    CpuFeatureScope scope(masm, FPU);
 
     Label no_update;
     Label skip_cache;
 
     // Call C function to calculate the result and update the cache.
     // a0: precalculated cache entry address.
     // a2 and a3: parts of the double value.
     // Store a0, a2 and a3 on stack for later before calling C function.
     __ Push(a3, a2, cache_entry);
     GenerateCallCFunction(masm, scratch0);
@@ skipping 107 matching lines @@
   __ TailCallRuntime(Runtime::kStackGuard, 0, 1);
 }
 
 
 void InterruptStub::Generate(MacroAssembler* masm) {
   __ TailCallRuntime(Runtime::kInterrupt, 0, 1);
 }
 
 
 void MathPowStub::Generate(MacroAssembler* masm) {
-  CpuFeatures::Scope fpu_scope(FPU);
+  CpuFeatureScope fpu_scope(masm, FPU);
   const Register base = a1;
   const Register exponent = a2;
   const Register heapnumbermap = t1;
   const Register heapnumber = v0;
   const DoubleRegister double_base = f2;
   const DoubleRegister double_exponent = f4;
   const DoubleRegister double_result = f0;
   const DoubleRegister double_scratch = f6;
   const FPURegister single_scratch = f8;
   const Register scratch = t5;
@@ skipping 222 matching lines @@
 
 void CodeStub::GenerateFPStubs(Isolate* isolate) {
   SaveFPRegsMode mode = CpuFeatures::IsSupported(FPU)
       ? kSaveFPRegs
       : kDontSaveFPRegs;
   CEntryStub save_doubles(1, mode);
   StoreBufferOverflowStub stub(mode);
   // These stubs might already be in the snapshot, detect that and don't
   // regenerate, which would lead to code stub initialization state being messed
   // up.
-  Code* save_doubles_code = NULL;
-  Code* store_buffer_overflow_code = NULL;
-  if (!save_doubles.FindCodeInCache(&save_doubles_code, ISOLATE)) {
-    if (CpuFeatures::IsSupported(FPU)) {
-      CpuFeatures::Scope scope2(FPU);
-      save_doubles_code = *save_doubles.GetCode(isolate);
-      store_buffer_overflow_code = *stub.GetCode(isolate);
-    } else {
-      save_doubles_code = *save_doubles.GetCode(isolate);
-      store_buffer_overflow_code = *stub.GetCode(isolate);
-    }
+  Code* save_doubles_code;
+  if (!save_doubles.FindCodeInCache(&save_doubles_code, isolate)) {
+    save_doubles_code = *save_doubles.GetCode(isolate);
     save_doubles_code->set_is_pregenerated(true);
+
+    Code* store_buffer_overflow_code = *stub.GetCode(isolate);
     store_buffer_overflow_code->set_is_pregenerated(true);
   }
-  ISOLATE->set_fp_stubs_generated(true);
+  isolate->set_fp_stubs_generated(true);
 }
 
 
 void CEntryStub::GenerateAheadOfTime(Isolate* isolate) {
   CEntryStub stub(1, kDontSaveFPRegs);
   Handle<Code> code = stub.GetCode(isolate);
   code->set_is_pregenerated(true);
 }
 
 
@@ skipping 235 matching lines @@
   // a3: argc
   //
   // Stack:
   // 4 args slots
   // args
 
   // Save callee saved registers on the stack.
   __ MultiPush(kCalleeSaved | ra.bit());
 
   if (CpuFeatures::IsSupported(FPU)) {
-    CpuFeatures::Scope scope(FPU);
+    CpuFeatureScope scope(masm, FPU);
     // Save callee-saved FPU registers.
     __ MultiPushFPU(kCalleeSavedFPU);
     // Set up the reserved register for 0.0.
     __ Move(kDoubleRegZero, 0.0);
   }
 
 
   // Load argv in s0 register.
   int offset_to_argv = (kNumCalleeSaved + 1) * kPointerSize;
   if (CpuFeatures::IsSupported(FPU)) {
@@ skipping 128 matching lines @@
   // Restore the top frame descriptors from the stack.
   __ pop(t1);
   __ li(t0, Operand(ExternalReference(Isolate::kCEntryFPAddress,
                                       isolate)));
   __ sw(t1, MemOperand(t0));
 
   // Reset the stack to the callee saved registers.
   __ addiu(sp, sp, -EntryFrameConstants::kCallerFPOffset);
 
   if (CpuFeatures::IsSupported(FPU)) {
-    CpuFeatures::Scope scope(FPU);
+    CpuFeatureScope scope(masm, FPU);
     // Restore callee-saved fpu registers.
     __ MultiPopFPU(kCalleeSavedFPU);
   }
 
   // Restore callee saved registers from the stack.
   __ MultiPop(kCalleeSaved | ra.bit());
   // Return.
   __ Jump(ra);
 }
 
@@ skipping 2671 matching lines @@
   if (left_ == CompareIC::SMI) {
     __ JumpIfNotSmi(a1, &miss);
   }
   if (right_ == CompareIC::SMI) {
     __ JumpIfNotSmi(a0, &miss);
   }
 
   // Inlining the double comparison and falling back to the general compare
   // stub if NaN is involved or FPU is unsupported.
   if (CpuFeatures::IsSupported(FPU)) {
-    CpuFeatures::Scope scope(FPU);
+    CpuFeatureScope scope(masm, FPU);
 
     // Load left and right operand.
     Label done, left, left_smi, right_smi;
     __ JumpIfSmi(a0, &right_smi);
     __ CheckMap(a0, a2, Heap::kHeapNumberMapRootIndex, &maybe_undefined1,
                 DONT_DO_SMI_CHECK);
     __ Subu(a2, a0, Operand(kHeapObjectTag));
     __ ldc1(f2, MemOperand(a2, HeapNumber::kValueOffset));
     __ Branch(&left);
     __ bind(&right_smi);
@@ skipping 988 matching lines @@
   __ Pop(ra, t1, a1);
   __ Ret();
 }
 
 
 #undef __
 
 } }  // namespace v8::internal
 
 #endif  // V8_TARGET_ARCH_MIPS