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Issue 12391055: Cleaned up CpuFeature scope handling. (Closed) Base URL: https://v8.googlecode.com/svn/branches/bleeding_edge
Patch Set: Fixed nits Created 7 years, 9 months ago
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1 // Copyright 2011 the V8 project authors. All rights reserved. 1 // Copyright 2011 the V8 project authors. All rights reserved.
2 // Redistribution and use in source and binary forms, with or without 2 // Redistribution and use in source and binary forms, with or without
3 // modification, are permitted provided that the following conditions are 3 // modification, are permitted provided that the following conditions are
4 // met: 4 // met:
5 // 5 //
6 // * Redistributions of source code must retain the above copyright 6 // * Redistributions of source code must retain the above copyright
7 // notice, this list of conditions and the following disclaimer. 7 // notice, this list of conditions and the following disclaimer.
8 // * Redistributions in binary form must reproduce the above 8 // * Redistributions in binary form must reproduce the above
9 // copyright notice, this list of conditions and the following 9 // copyright notice, this list of conditions and the following
10 // disclaimer in the documentation and/or other materials provided 10 // disclaimer in the documentation and/or other materials provided
(...skipping 306 matching lines...) Expand 10 before | Expand all | Expand 10 after
317 if (cgen_->IsInteger32(constant_source)) { 317 if (cgen_->IsInteger32(constant_source)) {
318 __ Set(dst, cgen_->ToInteger32Immediate(constant_source)); 318 __ Set(dst, cgen_->ToInteger32Immediate(constant_source));
319 } else { 319 } else {
320 Register tmp = EnsureTempRegister(); 320 Register tmp = EnsureTempRegister();
321 __ LoadObject(tmp, cgen_->ToHandle(constant_source)); 321 __ LoadObject(tmp, cgen_->ToHandle(constant_source));
322 __ mov(dst, tmp); 322 __ mov(dst, tmp);
323 } 323 }
324 } 324 }
325 325
326 } else if (source->IsDoubleRegister()) { 326 } else if (source->IsDoubleRegister()) {
327 CpuFeatures::Scope scope(SSE2); 327 CpuFeatureScope scope(cgen_->masm(), SSE2);
328 XMMRegister src = cgen_->ToDoubleRegister(source); 328 XMMRegister src = cgen_->ToDoubleRegister(source);
329 if (destination->IsDoubleRegister()) { 329 if (destination->IsDoubleRegister()) {
330 XMMRegister dst = cgen_->ToDoubleRegister(destination); 330 XMMRegister dst = cgen_->ToDoubleRegister(destination);
331 __ movaps(dst, src); 331 __ movaps(dst, src);
332 } else { 332 } else {
333 ASSERT(destination->IsDoubleStackSlot()); 333 ASSERT(destination->IsDoubleStackSlot());
334 Operand dst = cgen_->ToOperand(destination); 334 Operand dst = cgen_->ToOperand(destination);
335 __ movdbl(dst, src); 335 __ movdbl(dst, src);
336 } 336 }
337 } else if (source->IsDoubleStackSlot()) { 337 } else if (source->IsDoubleStackSlot()) {
338 CpuFeatures::Scope scope(SSE2); 338 CpuFeatureScope scope(cgen_->masm(), SSE2);
339 ASSERT(destination->IsDoubleRegister() || 339 ASSERT(destination->IsDoubleRegister() ||
340 destination->IsDoubleStackSlot()); 340 destination->IsDoubleStackSlot());
341 Operand src = cgen_->ToOperand(source); 341 Operand src = cgen_->ToOperand(source);
342 if (destination->IsDoubleRegister()) { 342 if (destination->IsDoubleRegister()) {
343 XMMRegister dst = cgen_->ToDoubleRegister(destination); 343 XMMRegister dst = cgen_->ToDoubleRegister(destination);
344 __ movdbl(dst, src); 344 __ movdbl(dst, src);
345 } else { 345 } else {
346 // We rely on having xmm0 available as a fixed scratch register. 346 // We rely on having xmm0 available as a fixed scratch register.
347 Operand dst = cgen_->ToOperand(destination); 347 Operand dst = cgen_->ToOperand(destination);
348 __ movdbl(xmm0, src); 348 __ movdbl(xmm0, src);
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404 __ xor_(src, tmp0); 404 __ xor_(src, tmp0);
405 __ xor_(tmp0, src); 405 __ xor_(tmp0, src);
406 __ mov(dst, tmp0); 406 __ mov(dst, tmp0);
407 } else { 407 } else {
408 __ mov(tmp0, dst); 408 __ mov(tmp0, dst);
409 __ mov(tmp1, src); 409 __ mov(tmp1, src);
410 __ mov(dst, tmp1); 410 __ mov(dst, tmp1);
411 __ mov(src, tmp0); 411 __ mov(src, tmp0);
412 } 412 }
413 } else if (source->IsDoubleRegister() && destination->IsDoubleRegister()) { 413 } else if (source->IsDoubleRegister() && destination->IsDoubleRegister()) {
414 CpuFeatures::Scope scope(SSE2); 414 CpuFeatureScope scope(cgen_->masm(), SSE2);
415 // XMM register-register swap. We rely on having xmm0 415 // XMM register-register swap. We rely on having xmm0
416 // available as a fixed scratch register. 416 // available as a fixed scratch register.
417 XMMRegister src = cgen_->ToDoubleRegister(source); 417 XMMRegister src = cgen_->ToDoubleRegister(source);
418 XMMRegister dst = cgen_->ToDoubleRegister(destination); 418 XMMRegister dst = cgen_->ToDoubleRegister(destination);
419 __ movaps(xmm0, src); 419 __ movaps(xmm0, src);
420 __ movaps(src, dst); 420 __ movaps(src, dst);
421 __ movaps(dst, xmm0); 421 __ movaps(dst, xmm0);
422 422
423 } else if (source->IsDoubleRegister() || destination->IsDoubleRegister()) { 423 } else if (source->IsDoubleRegister() || destination->IsDoubleRegister()) {
424 CpuFeatures::Scope scope(SSE2); 424 CpuFeatureScope scope(cgen_->masm(), SSE2);
425 // XMM register-memory swap. We rely on having xmm0 425 // XMM register-memory swap. We rely on having xmm0
426 // available as a fixed scratch register. 426 // available as a fixed scratch register.
427 ASSERT(source->IsDoubleStackSlot() || destination->IsDoubleStackSlot()); 427 ASSERT(source->IsDoubleStackSlot() || destination->IsDoubleStackSlot());
428 XMMRegister reg = cgen_->ToDoubleRegister(source->IsDoubleRegister() 428 XMMRegister reg = cgen_->ToDoubleRegister(source->IsDoubleRegister()
429 ? source 429 ? source
430 : destination); 430 : destination);
431 Operand other = 431 Operand other =
432 cgen_->ToOperand(source->IsDoubleRegister() ? destination : source); 432 cgen_->ToOperand(source->IsDoubleRegister() ? destination : source);
433 __ movdbl(xmm0, other); 433 __ movdbl(xmm0, other);
434 __ movdbl(other, reg); 434 __ movdbl(other, reg);
435 __ movdbl(reg, Operand(xmm0)); 435 __ movdbl(reg, Operand(xmm0));
436 436
437 } else if (source->IsDoubleStackSlot() && destination->IsDoubleStackSlot()) { 437 } else if (source->IsDoubleStackSlot() && destination->IsDoubleStackSlot()) {
438 CpuFeatures::Scope scope(SSE2); 438 CpuFeatureScope scope(cgen_->masm(), SSE2);
439 // Double-width memory-to-memory. Spill on demand to use a general 439 // Double-width memory-to-memory. Spill on demand to use a general
440 // purpose temporary register and also rely on having xmm0 available as 440 // purpose temporary register and also rely on having xmm0 available as
441 // a fixed scratch register. 441 // a fixed scratch register.
442 Register tmp = EnsureTempRegister(); 442 Register tmp = EnsureTempRegister();
443 Operand src0 = cgen_->ToOperand(source); 443 Operand src0 = cgen_->ToOperand(source);
444 Operand src1 = cgen_->HighOperand(source); 444 Operand src1 = cgen_->HighOperand(source);
445 Operand dst0 = cgen_->ToOperand(destination); 445 Operand dst0 = cgen_->ToOperand(destination);
446 Operand dst1 = cgen_->HighOperand(destination); 446 Operand dst1 = cgen_->HighOperand(destination);
447 __ movdbl(xmm0, dst0); // Save destination in xmm0. 447 __ movdbl(xmm0, dst0); // Save destination in xmm0.
448 __ mov(tmp, src0); // Then use tmp to copy source to destination. 448 __ mov(tmp, src0); // Then use tmp to copy source to destination.
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485 } else if (destination->IsRegister()) { 485 } else if (destination->IsRegister()) {
486 source_uses_[destination->index()] = CountSourceUses(destination); 486 source_uses_[destination->index()] = CountSourceUses(destination);
487 } 487 }
488 } 488 }
489 489
490 #undef __ 490 #undef __
491 491
492 } } // namespace v8::internal 492 } } // namespace v8::internal
493 493
494 #endif // V8_TARGET_ARCH_IA32 494 #endif // V8_TARGET_ARCH_IA32
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