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Issue 12391055: Cleaned up CpuFeature scope handling. (Closed) Base URL: https://v8.googlecode.com/svn/branches/bleeding_edge
Patch Set: Fixed nits Created 7 years, 9 months ago
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1 // Copyright 2012 the V8 project authors. All rights reserved. 1 // Copyright 2012 the V8 project authors. All rights reserved.
2 // Redistribution and use in source and binary forms, with or without 2 // Redistribution and use in source and binary forms, with or without
3 // modification, are permitted provided that the following conditions are 3 // modification, are permitted provided that the following conditions are
4 // met: 4 // met:
5 // 5 //
6 // * Redistributions of source code must retain the above copyright 6 // * Redistributions of source code must retain the above copyright
7 // notice, this list of conditions and the following disclaimer. 7 // notice, this list of conditions and the following disclaimer.
8 // * Redistributions in binary form must reproduce the above 8 // * Redistributions in binary form must reproduce the above
9 // copyright notice, this list of conditions and the following 9 // copyright notice, this list of conditions and the following
10 // disclaimer in the documentation and/or other materials provided 10 // disclaimer in the documentation and/or other materials provided
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970 970
971 Isolate* isolate = masm()->isolate(); 971 Isolate* isolate = masm()->isolate();
972 972
973 // Save all general purpose registers before messing with them. 973 // Save all general purpose registers before messing with them.
974 const int kNumberOfRegisters = Register::kNumRegisters; 974 const int kNumberOfRegisters = Register::kNumRegisters;
975 975
976 const int kDoubleRegsSize = kDoubleSize * 976 const int kDoubleRegsSize = kDoubleSize *
977 XMMRegister::kNumAllocatableRegisters; 977 XMMRegister::kNumAllocatableRegisters;
978 __ sub(esp, Immediate(kDoubleRegsSize)); 978 __ sub(esp, Immediate(kDoubleRegsSize));
979 if (CpuFeatures::IsSupported(SSE2)) { 979 if (CpuFeatures::IsSupported(SSE2)) {
980 CpuFeatures::Scope scope(SSE2); 980 CpuFeatureScope scope(masm(), SSE2);
981 for (int i = 0; i < XMMRegister::kNumAllocatableRegisters; ++i) { 981 for (int i = 0; i < XMMRegister::kNumAllocatableRegisters; ++i) {
982 XMMRegister xmm_reg = XMMRegister::FromAllocationIndex(i); 982 XMMRegister xmm_reg = XMMRegister::FromAllocationIndex(i);
983 int offset = i * kDoubleSize; 983 int offset = i * kDoubleSize;
984 __ movdbl(Operand(esp, offset), xmm_reg); 984 __ movdbl(Operand(esp, offset), xmm_reg);
985 } 985 }
986 } 986 }
987 987
988 __ pushad(); 988 __ pushad();
989 989
990 const int kSavedRegistersAreaSize = kNumberOfRegisters * kPointerSize + 990 const int kSavedRegistersAreaSize = kNumberOfRegisters * kPointerSize +
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1025 __ mov(ebx, Operand(eax, Deoptimizer::input_offset())); 1025 __ mov(ebx, Operand(eax, Deoptimizer::input_offset()));
1026 1026
1027 // Fill in the input registers. 1027 // Fill in the input registers.
1028 for (int i = kNumberOfRegisters - 1; i >= 0; i--) { 1028 for (int i = kNumberOfRegisters - 1; i >= 0; i--) {
1029 int offset = (i * kPointerSize) + FrameDescription::registers_offset(); 1029 int offset = (i * kPointerSize) + FrameDescription::registers_offset();
1030 __ pop(Operand(ebx, offset)); 1030 __ pop(Operand(ebx, offset));
1031 } 1031 }
1032 1032
1033 int double_regs_offset = FrameDescription::double_registers_offset(); 1033 int double_regs_offset = FrameDescription::double_registers_offset();
1034 if (CpuFeatures::IsSupported(SSE2)) { 1034 if (CpuFeatures::IsSupported(SSE2)) {
1035 CpuFeatures::Scope scope(SSE2); 1035 CpuFeatureScope scope(masm(), SSE2);
1036 // Fill in the double input registers. 1036 // Fill in the double input registers.
1037 for (int i = 0; i < XMMRegister::kNumAllocatableRegisters; ++i) { 1037 for (int i = 0; i < XMMRegister::kNumAllocatableRegisters; ++i) {
1038 int dst_offset = i * kDoubleSize + double_regs_offset; 1038 int dst_offset = i * kDoubleSize + double_regs_offset;
1039 int src_offset = i * kDoubleSize; 1039 int src_offset = i * kDoubleSize;
1040 __ movdbl(xmm0, Operand(esp, src_offset)); 1040 __ movdbl(xmm0, Operand(esp, src_offset));
1041 __ movdbl(Operand(ebx, dst_offset), xmm0); 1041 __ movdbl(Operand(ebx, dst_offset), xmm0);
1042 } 1042 }
1043 } 1043 }
1044 1044
1045 // Clear FPU all exceptions. 1045 // Clear FPU all exceptions.
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1126 __ bind(&inner_loop_header); 1126 __ bind(&inner_loop_header);
1127 __ test(ecx, ecx); 1127 __ test(ecx, ecx);
1128 __ j(not_zero, &inner_push_loop); 1128 __ j(not_zero, &inner_push_loop);
1129 __ add(eax, Immediate(kPointerSize)); 1129 __ add(eax, Immediate(kPointerSize));
1130 __ bind(&outer_loop_header); 1130 __ bind(&outer_loop_header);
1131 __ cmp(eax, edx); 1131 __ cmp(eax, edx);
1132 __ j(below, &outer_push_loop); 1132 __ j(below, &outer_push_loop);
1133 1133
1134 // In case of OSR or a failed STUB, we have to restore the XMM registers. 1134 // In case of OSR or a failed STUB, we have to restore the XMM registers.
1135 if (CpuFeatures::IsSupported(SSE2)) { 1135 if (CpuFeatures::IsSupported(SSE2)) {
1136 CpuFeatures::Scope scope(SSE2); 1136 CpuFeatureScope scope(masm(), SSE2);
1137 for (int i = 0; i < XMMRegister::kNumAllocatableRegisters; ++i) { 1137 for (int i = 0; i < XMMRegister::kNumAllocatableRegisters; ++i) {
1138 XMMRegister xmm_reg = XMMRegister::FromAllocationIndex(i); 1138 XMMRegister xmm_reg = XMMRegister::FromAllocationIndex(i);
1139 int src_offset = i * kDoubleSize + double_regs_offset; 1139 int src_offset = i * kDoubleSize + double_regs_offset;
1140 __ movdbl(xmm_reg, Operand(ebx, src_offset)); 1140 __ movdbl(xmm_reg, Operand(ebx, src_offset));
1141 } 1141 }
1142 } 1142 }
1143 1143
1144 // Push state, pc, and continuation from the last output frame. 1144 // Push state, pc, and continuation from the last output frame.
1145 if (type() != OSR) { 1145 if (type() != OSR) {
1146 __ push(Operand(ebx, FrameDescription::state_offset())); 1146 __ push(Operand(ebx, FrameDescription::state_offset()));
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1175 } 1175 }
1176 __ bind(&done); 1176 __ bind(&done);
1177 } 1177 }
1178 1178
1179 #undef __ 1179 #undef __
1180 1180
1181 1181
1182 } } // namespace v8::internal 1182 } } // namespace v8::internal
1183 1183
1184 #endif // V8_TARGET_ARCH_IA32 1184 #endif // V8_TARGET_ARCH_IA32
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