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| 1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file | 1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file |
| 2 // for details. All rights reserved. Use of this source code is governed by a | 2 // for details. All rights reserved. Use of this source code is governed by a |
| 3 // BSD-style license that can be found in the LICENSE file. | 3 // BSD-style license that can be found in the LICENSE file. |
| 4 | 4 |
| 5 #ifndef VM_CONSTANTS_ARM_H_ | 5 #ifndef VM_CONSTANTS_ARM_H_ |
| 6 #define VM_CONSTANTS_ARM_H_ | 6 #define VM_CONSTANTS_ARM_H_ |
| 7 | 7 |
| 8 namespace dart { | 8 namespace dart { |
| 9 | 9 |
| 10 // We support both VFPv3-D16 and VFPv3-D32 profiles, but currently only one at | 10 // We support both VFPv3-D16 and VFPv3-D32 profiles, but currently only one at |
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| 268 kOffset12Shift = 0, | 268 kOffset12Shift = 0, |
| 269 kOffset12Bits = 12, | 269 kOffset12Bits = 12, |
| 270 kOffset12Mask = 0x00000fff, | 270 kOffset12Mask = 0x00000fff, |
| 271 | 271 |
| 272 // Mul instruction register fields encodings. | 272 // Mul instruction register fields encodings. |
| 273 kMulRdShift = 16, | 273 kMulRdShift = 16, |
| 274 kMulRdBits = 4, | 274 kMulRdBits = 4, |
| 275 kMulRnShift = 12, | 275 kMulRnShift = 12, |
| 276 kMulRnBits = 4, | 276 kMulRnBits = 4, |
| 277 | 277 |
| 278 // MRC instruction offset field encoding | |
|
srdjan
2013/03/04 22:02:17
ditto
| |
| 279 kCRmShift = 0, | |
| 280 kCRmBits = 4, | |
| 281 kOpc2Shift = 5, | |
| 282 kOpc2Bits = 3, | |
| 283 kCoprocShift = 8, | |
| 284 kCoprocBits = 4, | |
| 285 kCRnShift = 16, | |
| 286 kCRnBits = 4, | |
| 287 kOpc1Shift = 21, | |
| 288 kOpc1Bits = 3, | |
| 289 | |
| 278 kBranchOffsetMask = 0x00ffffff | 290 kBranchOffsetMask = 0x00ffffff |
| 279 }; | 291 }; |
| 280 | 292 |
| 281 | 293 |
| 282 // The class Instr enables access to individual fields defined in the ARM | 294 // The class Instr enables access to individual fields defined in the ARM |
| 283 // architecture instruction set encoding as described in figure A3-1. | 295 // architecture instruction set encoding as described in figure A3-1. |
| 284 // | 296 // |
| 285 // Example: Test whether the instruction at ptr sets the condition code bits. | 297 // Example: Test whether the instruction at ptr sets the condition code bits. |
| 286 // | 298 // |
| 287 // bool InstructionSetsConditionCodes(byte* ptr) { | 299 // bool InstructionSetsConditionCodes(byte* ptr) { |
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| 479 ((Bits(4, 4) & 0xd) == 1)); | 491 ((Bits(4, 4) & 0xd) == 1)); |
| 480 } | 492 } |
| 481 | 493 |
| 482 // Test for VFP load and store instructions of type 6. | 494 // Test for VFP load and store instructions of type 6. |
| 483 inline bool IsVFPLoadStore() const { | 495 inline bool IsVFPLoadStore() const { |
| 484 ASSERT(ConditionField() != kSpecialCondition); | 496 ASSERT(ConditionField() != kSpecialCondition); |
| 485 ASSERT(TypeField() == 6); | 497 ASSERT(TypeField() == 6); |
| 486 return ((Bits(20, 5) & 0x12) == 0x10) && (Bits(9, 3) == 5); | 498 return ((Bits(20, 5) & 0x12) == 0x10) && (Bits(9, 3) == 5); |
| 487 } | 499 } |
| 488 | 500 |
| 501 // Only handle mrc of the id_isar0 register. | |
| 502 inline bool IsMrcIdIsar0() const { | |
| 503 ASSERT(ConditionField() != kSpecialCondition); | |
| 504 ASSERT(TypeField() == 7); | |
| 505 return (Bits(21, 3) == 0) && (Bits(16, 4) == 0) && | |
| 506 (Bits(8, 4) == 0xf) && (Bits(5, 3) == 0) && | |
| 507 (Bits(0, 4) == 2); | |
| 508 } | |
| 509 | |
| 489 // Test for VFP multiple load and store instructions of type 6. | 510 // Test for VFP multiple load and store instructions of type 6. |
| 490 inline bool IsVFPMultipleLoadStore() const { | 511 inline bool IsVFPMultipleLoadStore() const { |
| 491 ASSERT(ConditionField() != kSpecialCondition); | 512 ASSERT(ConditionField() != kSpecialCondition); |
| 492 ASSERT(TypeField() == 6); | 513 ASSERT(TypeField() == 6); |
| 493 int32_t puw = (PUField() << 1) | Bit(21); // don't care about D bit | 514 int32_t puw = (PUField() << 1) | Bit(21); // don't care about D bit |
| 494 return (Bits(9, 3) == 5) && ((puw == 2) || (puw == 3) || (puw == 5)); | 515 return (Bits(9, 3) == 5) && ((puw == 2) || (puw == 3) || (puw == 5)); |
| 495 } | 516 } |
| 496 | 517 |
| 497 // Special accessors that test for existence of a value. | 518 // Special accessors that test for existence of a value. |
| 498 inline bool HasS() const { return SField() == 1; } | 519 inline bool HasS() const { return SField() == 1; } |
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| 511 Instr* Next() { return this + kInstrSize; } | 532 Instr* Next() { return this + kInstrSize; } |
| 512 | 533 |
| 513 private: | 534 private: |
| 514 DISALLOW_ALLOCATION(); | 535 DISALLOW_ALLOCATION(); |
| 515 DISALLOW_IMPLICIT_CONSTRUCTORS(Instr); | 536 DISALLOW_IMPLICIT_CONSTRUCTORS(Instr); |
| 516 }; | 537 }; |
| 517 | 538 |
| 518 } // namespace dart | 539 } // namespace dart |
| 519 | 540 |
| 520 #endif // VM_CONSTANTS_ARM_H_ | 541 #endif // VM_CONSTANTS_ARM_H_ |
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