ARM backend support for pld (preload data) instruction

src/arm/disasm-arm.cc

 // Copyright 2011 the V8 project authors. All rights reserved.
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions are
 // met:
 //
 //     * Redistributions of source code must retain the above copyright
 //       notice, this list of conditions and the following disclaimer.
 //     * Redistributions in binary form must reproduce the above
 //       copyright notice, this list of conditions and the following
 //       disclaimer in the documentation and/or other materials provided
@@ skipping 539 matching lines @@
         return 15;
       }
       // 'off8: 8-bit offset for extra load and store instructions
       ASSERT(STRING_STARTS_WITH(format, "off8"));
       int offs8 = (instr->ImmedHValue() << 4) | instr->ImmedLValue();
       out_buffer_pos_ += OS::SNPrintF(out_buffer_ + out_buffer_pos_,
                                       "%d", offs8);
       return 4;
     }
     case 'p': {  // 'pu: P and U bits for load and store instructions
-      ASSERT(STRING_STARTS_WITH(format, "pu"));
-      PrintPU(instr);
-      return 2;
+      if (STRING_STARTS_WITH(format, "pu")) {
+        PrintPU(instr);
+        return 2;
+      } else {
+        ASSERT(STRING_STARTS_WITH(format, "preload"));
+        Print("pld");
+        return 7;
+      }
     }
     case 'r': {
       return FormatRegister(instr, format);
     }
     case 's': {
       if (format[1] == 'h') {  // 'shift_op or 'shift_rm or 'shift_sat.
         if (format[6] == 'o') {  // 'shift_op
           ASSERT(STRING_STARTS_WITH(format, "shift_op"));
           if (instr->TypeValue() == 0) {
             PrintShiftRm(instr);
@@ skipping 376 matching lines @@
     }
     case ia_x: {
       if (instr->HasW()) {
         Unknown(instr);  // not used in V8
         return;
       }
       Format(instr, "'memop'cond'b 'rd, ['rn], #+'off12");
       break;
     }
     case db_x: {
-      Format(instr, "'memop'cond'b 'rd, ['rn, #-'off12]'w");
+      if (instr->ConditionField() == kSpecialCondition) {
+        Format(instr, "'preload ['rn, #-'off12]");
+      } else {
+        Format(instr, "'memop'cond'b 'rd, ['rn, #-'off12]'w");
+      }
       break;
     }
     case ib_x: {
-      Format(instr, "'memop'cond'b 'rd, ['rn, #+'off12]'w");
+      if (instr->ConditionField() == kSpecialCondition) {
+        Format(instr, "'preload ['rn, #+'off12]");
+      } else {
+        Format(instr, "'memop'cond'b 'rd, ['rn, #+'off12]'w");
+      }
       break;
     }
     default: {
       // The PU field is a 2-bit field.
       UNREACHABLE();
       break;
     }
   }
 }
 
@@ skipping 23 matching lines @@
         if (!instr->HasW()) {
           if (instr->Bits(5, 4) == 0x1) {
             if ((instr->Bit(22) == 0x0) && (instr->Bit(20) == 0x1)) {
               // SDIV (in V8 notation matching ARM ISA format) rn = rm/rs
               Format(instr, "sdiv'cond'b 'rn, 'rm, 'rs");
               break;
             }
           }
         }
       }
-      Format(instr, "'memop'cond'b 'rd, ['rn, -'shift_rm]'w");
+      if (instr->ConditionField() == kSpecialCondition) {
+        Format(instr, "'preload ['rn, -'shift_rm]");
+      } else {
+        Format(instr, "'memop'cond'b 'rd, ['rn, -'shift_rm]'w");
+      }
       break;
     }
     case ib_x: {
       if (instr->HasW() && (instr->Bits(6, 4) == 0x5)) {
         uint32_t widthminus1 = static_cast<uint32_t>(instr->Bits(20, 16));
         uint32_t lsbit = static_cast<uint32_t>(instr->Bits(11, 7));
         uint32_t msbit = widthminus1 + lsbit;
         if (msbit <= 31) {
           if (instr->Bit(22)) {
             Format(instr, "ubfx'cond 'rd, 'rm, 'f");
           } else {
             Format(instr, "sbfx'cond 'rd, 'rm, 'f");
           }
         } else {
           UNREACHABLE();
         }
       } else if (!instr->HasW() && (instr->Bits(6, 4) == 0x1)) {
         uint32_t lsbit = static_cast<uint32_t>(instr->Bits(11, 7));
         uint32_t msbit = static_cast<uint32_t>(instr->Bits(20, 16));
         if (msbit >= lsbit) {
           if (instr->RmValue() == 15) {
             Format(instr, "bfc'cond 'rd, 'f");
           } else {
             Format(instr, "bfi'cond 'rd, 'rm, 'f");
           }
         } else {
           UNREACHABLE();
         }
+      } else if (instr->ConditionField() == kSpecialCondition) {
+        Format(instr, "'preload ['rn, +'shift_rm]");
       } else {
         Format(instr, "'memop'cond'b 'rd, ['rn, +'shift_rm]'w");
       }
       break;
     }
     default: {
       // The PU field is a 2-bit field.
       UNREACHABLE();
       break;
     }
@@ skipping 378 matching lines @@
 }
 
 
 // Disassemble the instruction at *instr_ptr into the output buffer.
 int Decoder::InstructionDecode(byte* instr_ptr) {
   Instruction* instr = Instruction::At(instr_ptr);
   // Print raw instruction bytes.
   out_buffer_pos_ += OS::SNPrintF(out_buffer_ + out_buffer_pos_,
                                   "%08x       ",
                                   instr->InstructionBits());
-  if (instr->ConditionField() == kSpecialCondition) {
+  if (instr->ConditionField() == kSpecialCondition && !instr->IsPld()) {
     Unknown(instr);
     return Instruction::kInstrSize;
   }
   int instruction_bits = *(reinterpret_cast<int*>(instr_ptr));
   if ((instruction_bits & kConstantPoolMarkerMask) == kConstantPoolMarker) {
     out_buffer_pos_ += OS::SNPrintF(out_buffer_ + out_buffer_pos_,
                                     "constant pool begin (length %d)",
                                     DecodeConstantPoolLength(instruction_bits));
     return Instruction::kInstrSize;
   }
@@ skipping 111 matching lines @@
     pc += d.InstructionDecode(buffer, pc);
     fprintf(f, "%p    %08x      %s\n",
             prev_pc, *reinterpret_cast<int32_t*>(prev_pc), buffer.start());
   }
 }
 
 
 }  // namespace disasm
 
 #endif  // V8_TARGET_ARCH_ARM