ARM backend support for pld (preload data) instruction

test/cctest/test-disasm-arm.cc

 // Copyright 2011 the V8 project authors. All rights reserved.
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions are
 // met:
 //
 //     * Redistributions of source code must retain the above copyright
 //       notice, this list of conditions and the following disclaimer.
 //     * Redistributions in binary form must reproduce the above
 //       copyright notice, this list of conditions and the following
 //       disclaimer in the documentation and/or other materials provided
@@ skipping 845 matching lines @@
     COMPARE(strd(r8, r9, MemOperand(r9, -127, PostIndex)),
             "e04987ff       strd r8, [r9], #-127");
     COMPARE(strd(r10, fp, MemOperand(fp, 127, PreIndex)),
             "e1eba7ff       strd r10, [fp, #+127]!");
     COMPARE(strd(ip, sp, MemOperand(sp, -127, PreIndex)),
             "e16dc7ff       strd ip, [sp, #-127]!");
   }
 
   VERIFY_RUN();
 }
+
+
+TEST(Preload) {
+  SET_UP();
+
+  COMPARE(pld(MemOperand(r1)),
+          "f5d1f000       pld [r1, #+0]");
+  COMPARE(pld(MemOperand(r2, 4)),
+          "f5d2f004       pld [r2, #+4]");
+  COMPARE(pld(MemOperand(r3, -8)),
+          "f553f008       pld [r3, #-8]");
+  COMPARE(pld(MemOperand(r1, r2)),
+          "f7d1f002       pld [r1, +r2]");
+  COMPARE(pld(MemOperand(r4, r5, NegOffset)),
+          "f754f005       pld [r4, -r5]");
+  COMPARE(pld(MemOperand(r1, r2, ASR, 2)),
+          "f7d1f142       pld [r1, +r2, asr #2]");
+  COMPARE(pld(MemOperand(r3, r4, LSL, 8, NegOffset)),
+          "f753f404       pld [r3, -r4, lsl #8]");
+
+  VERIFY_RUN();
+}
+