Factor out legalization of undef, and handle more cases for ARM.

tests_lit/llvm2ice_tests/undef.ll

 ; This test checks that undef values are represented as zero.
 
 ; RUN: %p2i -i %s --filetype=obj --disassemble --args -O2 \
 ; RUN:   | FileCheck %s
 ; RUN: %p2i -i %s --filetype=obj --disassemble --args -Om1 \
 ; RUN:   | FileCheck %s
 ; RUN: %p2i -i %s --filetype=obj --disassemble --args -O2 -mattr=sse4.1 \
 ; RUN:   | FileCheck %s
 ; RUN: %p2i -i %s --filetype=obj --disassemble --args -Om1 -mattr=sse4.1 \
 ; RUN:   | FileCheck %s
 
 define i32 @undef_i32() {
 entry:
   ret i32 undef
 ; CHECK-LABEL: undef_i32
 ; CHECK: mov eax,0x0
 }
 
 define i64 @undef_i64() {
 entry:
   ret i64 undef
 ; CHECK-LABEL: undef_i64
 ; CHECK-DAG: mov eax,0x0
 ; CHECK-DAG: mov edx,0x0
 ; CHECK: ret
 }
 
+define i32 @trunc_undef_i64() {
+entry:
+  %ret = trunc i64 undef to i32
+  ret i32 %ret
+; CHECK-LABEL: trunc_undef_i64
+; CHECK: mov eax,0x0
+; CHECK: ret
+}
+
 define float @undef_float() {
 entry:
   ret float undef
 ; CHECK-LABEL: undef_float
 ; CHECK: fld DWORD PTR {{.*}} .L$float$0
 }
 
 define <4 x i1> @undef_v4i1() {
 entry:
   ret <4 x i1> undef
@@ skipping 236 matching lines @@
 ; CHECK: pxor
 }
 
 define <4 x float> @vector_select_v4f32_arg2(<4 x i1> %cond, <4 x float> %a) {
 entry:
   %val = select <4 x i1> %cond, <4 x float> %a, <4 x float> undef
   ret <4 x float> %val
 ; CHECK-LABEL: vector_select_v4f32_arg2
 ; CHECK: pxor
 }