Factor out legalization of undef, and handle more cases for ARM.

tests_lit/llvm2ice_tests/nacl-other-intrinsics.ll

 ; This tests the NaCl intrinsics not related to atomic operations.
 
 ; RUN: %if --need=target_X8632 --command %p2i --filetype=obj --disassemble \
 ; RUN:   --target x8632 -i %s --args -O2 -sandbox \
 ; RUN:   | %if --need=target_X8632 --command FileCheck %s
 ; RUN: %if --need=target_X8632 --command %p2i --filetype=obj --disassemble \
 ; RUN:   --target x8632 -i %s --args -Om1 -sandbox \
 ; RUN:   | %if --need=target_X8632 --command FileCheck %s
 
 ; Do another run w/ O2 and a different check-prefix (otherwise O2 and Om1
@@ skipping 398 matching lines @@
   %r = call i64 @llvm.bswap.i64(i64 %x)
   ret i64 %r
 }
 ; CHECK-LABEL: test_bswap_64
 ; CHECK: bswap e{{.*}}
 ; CHECK: bswap e{{.*}}
 ; ARM32-LABEL: test_bswap_64
 ; ARM32: rev
 ; ARM32: rev
 
+define i64 @test_bswap_64_undef() {
+entry:
+  %r = call i64 @llvm.bswap.i64(i64 undef)
+  ret i64 %r
+}
+; CHECK-LABEL: test_bswap_64_undef
+; CHECK: bswap e{{.*}}
+; CHECK: bswap e{{.*}}
+; ARM32-LABEL: test_bswap_64
+; ARM32: rev
+; ARM32: rev
+
 define i32 @test_ctlz_32(i32 %x) {
 entry:
   %r = call i32 @llvm.ctlz.i32(i32 %x, i1 false)
   ret i32 %r
 }
 ; CHECK-LABEL: test_ctlz_32
 ; TODO(jvoung): If we detect that LZCNT is supported, then use that
 ; and avoid the need to do the cmovne and xor stuff to guarantee that
 ; the result is well-defined w/ input == 0.
 ; CHECK: bsr [[REG_TMP:e.*]],{{.*}}
@@ skipping 185 matching lines @@
 ; At least 3 copies of esp, but probably more from having to do the allocas.
 ; CHECK: mov {{.*}},esp
 ; CHECK: mov {{.*}},esp
 ; CHECK: mov {{.*}},esp
 ; CHECK: mov esp,{{.*}}
 ; ARM32-LABEL: test_stacksave_multiple
 ; ARM32: mov {{.*}}, sp
 ; ARM32: mov {{.*}}, sp
 ; ARM32: mov {{.*}}, sp
 ; ARM32: mov sp, {{.*}}