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1 ; This tests each of the supported NaCl atomic instructions for every | 1 ; This tests each of the supported NaCl atomic instructions for every |
2 ; size allowed. | 2 ; size allowed. |
3 | 3 |
4 ; RUN: %p2i -i %s --filetype=obj --disassemble --args -O2 \ | 4 ; RUN: %p2i -i %s --filetype=obj --disassemble --args -O2 \ |
5 ; RUN: | FileCheck %s | 5 ; RUN: | FileCheck %s |
6 ; RUN: %p2i -i %s --filetype=obj --disassemble --args -O2 \ | 6 ; RUN: %p2i -i %s --filetype=obj --disassemble --args -O2 \ |
7 ; RUN: | FileCheck --check-prefix=O2 %s | 7 ; RUN: | FileCheck --check-prefix=O2 %s |
8 ; RUN: %p2i -i %s --filetype=obj --disassemble --args -Om1 \ | 8 ; RUN: %p2i -i %s --filetype=obj --disassemble --args -Om1 \ |
9 ; RUN: | FileCheck %s | 9 ; RUN: | FileCheck %s |
10 | 10 |
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764 ; CHECK: push ebx | 764 ; CHECK: push ebx |
765 ; CHECK-DAG: mov edx | 765 ; CHECK-DAG: mov edx |
766 ; CHECK-DAG: mov eax | 766 ; CHECK-DAG: mov eax |
767 ; CHECK-DAG: mov ecx | 767 ; CHECK-DAG: mov ecx |
768 ; CHECK-DAG: mov ebx | 768 ; CHECK-DAG: mov ebx |
769 ; CHECK: lock cmpxchg8b QWORD PTR [e{{.[^x]}}+0x0] | 769 ; CHECK: lock cmpxchg8b QWORD PTR [e{{.[^x]}}+0x0] |
770 ; edx and eax are already the return registers, so they don't actually | 770 ; edx and eax are already the return registers, so they don't actually |
771 ; need to be reshuffled via movs. The next test stores the result | 771 ; need to be reshuffled via movs. The next test stores the result |
772 ; somewhere, so in that case they do need to be mov'ed. | 772 ; somewhere, so in that case they do need to be mov'ed. |
773 | 773 |
| 774 define i64 @test_atomic_cmpxchg_64_undef(i32 %iptr, i64 %desired) { |
| 775 entry: |
| 776 %ptr = inttoptr i32 %iptr to i64* |
| 777 %old = call i64 @llvm.nacl.atomic.cmpxchg.i64(i64* %ptr, i64 undef, |
| 778 i64 %desired, i32 6, i32 6) |
| 779 ret i64 %old |
| 780 } |
| 781 ; CHECK-LABEL: test_atomic_cmpxchg_64_undef |
| 782 ; CHECK: lock cmpxchg8b QWORD PTR [e{{.[^x]}}+0x0] |
| 783 |
774 ; Test a case where %old really does need to be copied out of edx:eax. | 784 ; Test a case where %old really does need to be copied out of edx:eax. |
775 define void @test_atomic_cmpxchg_64_store(i32 %ret_iptr, i32 %iptr, i64 %expecte
d, i64 %desired) { | 785 define void @test_atomic_cmpxchg_64_store(i32 %ret_iptr, i32 %iptr, i64 %expecte
d, i64 %desired) { |
776 entry: | 786 entry: |
777 %ptr = inttoptr i32 %iptr to i64* | 787 %ptr = inttoptr i32 %iptr to i64* |
778 %old = call i64 @llvm.nacl.atomic.cmpxchg.i64(i64* %ptr, i64 %expected, | 788 %old = call i64 @llvm.nacl.atomic.cmpxchg.i64(i64* %ptr, i64 %expected, |
779 i64 %desired, i32 6, i32 6) | 789 i64 %desired, i32 6, i32 6) |
780 %__6 = inttoptr i32 %ret_iptr to i64* | 790 %__6 = inttoptr i32 %ret_iptr to i64* |
781 store i64 %old, i64* %__6, align 1 | 791 store i64 %old, i64* %__6, align 1 |
782 ret void | 792 ret void |
783 } | 793 } |
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1002 br i1 %cmp, label %done, label %body | 1012 br i1 %cmp, label %done, label %body |
1003 done: | 1013 done: |
1004 ret void | 1014 ret void |
1005 } | 1015 } |
1006 ; O2-LABEL: test_cmpxchg8b_regalloc | 1016 ; O2-LABEL: test_cmpxchg8b_regalloc |
1007 ;;; eax and some other register will be used in the cmpxchg instruction. | 1017 ;;; eax and some other register will be used in the cmpxchg instruction. |
1008 ; O2: lock cmpxchg8b QWORD PTR | 1018 ; O2: lock cmpxchg8b QWORD PTR |
1009 ;;; Make sure eax/ecx/edx/ebx aren't used again, e.g. as the induction variable. | 1019 ;;; Make sure eax/ecx/edx/ebx aren't used again, e.g. as the induction variable. |
1010 ; O2-NOT: {{eax|ecx|edx|ebx}} | 1020 ; O2-NOT: {{eax|ecx|edx|ebx}} |
1011 ; O2: pop ebx | 1021 ; O2: pop ebx |
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