Factor out legalization of undef, and handle more cases for ARM.

src/IceTargetLoweringARM32.cpp

 //===- subzero/src/IceTargetLoweringARM32.cpp - ARM32 lowering ------------===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 845 matching lines @@
   if (Var->getIsArg()) {
     Lo->setIsArg();
     Hi->setIsArg();
   }
 }
 
 Operand *TargetARM32::loOperand(Operand *Operand) {
   assert(Operand->getType() == IceType_i64);
   if (Operand->getType() != IceType_i64)
     return Operand;
-  if (Variable *Var = llvm::dyn_cast<Variable>(Operand)) {
+  if (auto *Var = llvm::dyn_cast<Variable>(Operand)) {
     split64(Var);
     return Var->getLo();
   }
-  if (ConstantInteger64 *Const = llvm::dyn_cast<ConstantInteger64>(Operand)) {
+  if (auto *Const = llvm::dyn_cast<ConstantInteger64>(Operand)) {
     return Ctx->getConstantInt32(static_cast<uint32_t>(Const->getValue()));
   }
-  if (OperandARM32Mem *Mem = llvm::dyn_cast<OperandARM32Mem>(Operand)) {
+  if (auto *Mem = llvm::dyn_cast<OperandARM32Mem>(Operand)) {
     // Conservatively disallow memory operands with side-effects (pre/post
     // increment) in case of duplication.
     assert(Mem->getAddrMode() == OperandARM32Mem::Offset ||
            Mem->getAddrMode() == OperandARM32Mem::NegOffset);
     if (Mem->isRegReg()) {
       return OperandARM32Mem::create(Func, IceType_i32, Mem->getBase(),
                                      Mem->getIndex(), Mem->getShiftOp(),
                                      Mem->getShiftAmt(), Mem->getAddrMode());
     } else {
       return OperandARM32Mem::create(Func, IceType_i32, Mem->getBase(),
                                      Mem->getOffset(), Mem->getAddrMode());
     }
   }
   llvm_unreachable("Unsupported operand type");
   return nullptr;
 }
 
 Operand *TargetARM32::hiOperand(Operand *Operand) {
   assert(Operand->getType() == IceType_i64);
   if (Operand->getType() != IceType_i64)
     return Operand;
-  if (Variable *Var = llvm::dyn_cast<Variable>(Operand)) {
+  if (auto *Var = llvm::dyn_cast<Variable>(Operand)) {
     split64(Var);
     return Var->getHi();
   }
-  if (ConstantInteger64 *Const = llvm::dyn_cast<ConstantInteger64>(Operand)) {
+  if (auto *Const = llvm::dyn_cast<ConstantInteger64>(Operand)) {
     return Ctx->getConstantInt32(
         static_cast<uint32_t>(Const->getValue() >> 32));
   }
-  if (OperandARM32Mem *Mem = llvm::dyn_cast<OperandARM32Mem>(Operand)) {
+  if (auto *Mem = llvm::dyn_cast<OperandARM32Mem>(Operand)) {
     // Conservatively disallow memory operands with side-effects
     // in case of duplication.
     assert(Mem->getAddrMode() == OperandARM32Mem::Offset ||
            Mem->getAddrMode() == OperandARM32Mem::NegOffset);
     const Type SplitType = IceType_i32;
     if (Mem->isRegReg()) {
       // We have to make a temp variable T, and add 4 to either Base or Index.
       // The Index may be shifted, so adding 4 can mean something else.
       // Thus, prefer T := Base + 4, and use T as the new Base.
       Variable *Base = Mem->getBase();
@@ skipping 91 matching lines @@
   Operand *TotalSize = Inst->getSizeInBytes();
   if (const auto *ConstantTotalSize =
           llvm::dyn_cast<ConstantInteger32>(TotalSize)) {
     uint32_t Value = ConstantTotalSize->getValue();
     Value = Utils::applyAlignment(Value, Alignment);
     Operand *SubAmount = legalize(Ctx->getConstantInt32(Value));
     _sub(SP, SP, SubAmount);
   } else {
     // Non-constant sizes need to be adjusted to the next highest
     // multiple of the required alignment at runtime.
-    TotalSize = legalize(TotalSize);
+    TotalSize = legalize(TotalSize, Legal_Reg | Legal_Flex);
     Variable *T = makeReg(IceType_i32);
     _mov(T, TotalSize);
     Operand *AddAmount = legalize(Ctx->getConstantInt32(Alignment - 1));
     _add(T, T, AddAmount);
     alignRegisterPow2(T, Alignment);
     _sub(SP, SP, T);
   }
   _mov(Dest, SP);
 }
 
@@ skipping 68 matching lines @@
 
 void TargetARM32::lowerArithmetic(const InstArithmetic *Inst) {
   Variable *Dest = Inst->getDest();
   // TODO(jvoung): Should be able to flip Src0 and Src1 if it is easier
   // to legalize Src0 to flex or Src1 to flex and there is a reversible
   // instruction. E.g., reverse subtract with immediate, register vs
   // register, immediate.
   // Or it may be the case that the operands aren't swapped, but the
   // bits can be flipped and a different operation applied.
   // E.g., use BIC (bit clear) instead of AND for some masks.
-  Operand *Src0 = Inst->getSrc(0);
-  Operand *Src1 = Inst->getSrc(1);
+  Operand *Src0 = legalizeUndef(Inst->getSrc(0));
+  Operand *Src1 = legalizeUndef(Inst->getSrc(1));
   if (Dest->getType() == IceType_i64) {
     // These helper-call-involved instructions are lowered in this
     // separate switch. This is because we would otherwise assume that
     // we need to legalize Src0 to Src0RLo and Src0Hi. However, those go unused
     // with helper calls, and such unused/redundant instructions will fail
     // liveness analysis under -Om1 setting.
     switch (Inst->getOp()) {
     default:
       break;
     case InstArithmetic::Udiv:
@@ skipping 335 matching lines @@
     UnimplementedError(Func->getContext()->getFlags());
     return;
   }
 }
 
 void TargetARM32::lowerAssign(const InstAssign *Inst) {
   Variable *Dest = Inst->getDest();
   Operand *Src0 = Inst->getSrc(0);
   assert(Dest->getType() == Src0->getType());
   if (Dest->getType() == IceType_i64) {
-    Src0 = legalize(Src0);
-    Operand *Src0Lo = loOperand(Src0);
-    Operand *Src0Hi = hiOperand(Src0);
+    Src0 = legalizeUndef(Src0);
+    Operand *Src0Lo = legalize(loOperand(Src0), Legal_Reg | Legal_Flex);
+    Operand *Src0Hi = legalize(hiOperand(Src0), Legal_Reg | Legal_Flex);
     Variable *DestLo = llvm::cast<Variable>(loOperand(Dest));
     Variable *DestHi = llvm::cast<Variable>(hiOperand(Dest));
     Variable *T_Lo = nullptr, *T_Hi = nullptr;
     _mov(T_Lo, Src0Lo);
     _mov(DestLo, T_Lo);
     _mov(T_Hi, Src0Hi);
     _mov(DestHi, T_Hi);
   } else {
     Operand *SrcR;
     if (Dest->hasReg()) {
@@ skipping 42 matching lines @@
   // Pair of Arg Operand -> GPR number assignments.
   llvm::SmallVector<std::pair<Operand *, int32_t>,
                     TargetARM32::CallingConv::ARM32_MAX_GPR_ARG> GPRArgs;
   // Pair of Arg Operand -> stack offset.
   llvm::SmallVector<std::pair<Operand *, int32_t>, 8> StackArgs;
   int32_t ParameterAreaSizeBytes = 0;
 
   // Classify each argument operand according to the location where the
   // argument is passed.
   for (SizeT i = 0, NumArgs = Instr->getNumArgs(); i < NumArgs; ++i) {
-    Operand *Arg = Instr->getArg(i);
+    Operand *Arg = legalizeUndef(Instr->getArg(i));
     Type Ty = Arg->getType();
     bool InRegs = false;
     if (isVectorType(Ty)) {
       UnimplementedError(Func->getContext()->getFlags());
     } else if (isFloatingType(Ty)) {
       UnimplementedError(Func->getContext()->getFlags());
     } else if (Ty == IceType_i64) {
       std::pair<int32_t, int32_t> Regs;
       if (CC.I64InRegs(&Regs)) {
         InRegs = true;
@@ skipping 159 matching lines @@
       } else {
         _mov(Dest, ReturnReg);
       }
     }
   }
 }
 
 void TargetARM32::lowerCast(const InstCast *Inst) {
   InstCast::OpKind CastKind = Inst->getCastKind();
   Variable *Dest = Inst->getDest();
-  Operand *Src0 = Inst->getSrc(0);
+  Operand *Src0 = legalizeUndef(Inst->getSrc(0));
   switch (CastKind) {
   default:
     Func->setError("Cast type not supported");
     return;
   case InstCast::Sext: {
     if (isVectorType(Dest->getType())) {
       UnimplementedError(Func->getContext()->getFlags());
     } else if (Dest->getType() == IceType_i64) {
       // t1=sxtb src; t2= mov t1 asr #31; dst.lo=t1; dst.hi=t2
       Constant *ShiftAmt = Ctx->getConstantInt32(31);
@@ skipping 84 matching lines @@
       Variable *T = makeReg(Dest->getType());
       _uxt(T, Src0R);
       _mov(Dest, T);
     }
     break;
   }
   case InstCast::Trunc: {
     if (isVectorType(Dest->getType())) {
       UnimplementedError(Func->getContext()->getFlags());
     } else {
-      Operand *Src0 = Inst->getSrc(0);
       if (Src0->getType() == IceType_i64)
         Src0 = loOperand(Src0);
       Operand *Src0RF = legalize(Src0, Legal_Reg | Legal_Flex);
       // t1 = trunc Src0RF; Dest = t1
       Variable *T = makeReg(Dest->getType());
       _mov(T, Src0RF);
       if (Dest->getType() == IceType_i1)
         _and(T, T, Ctx->getConstantInt1(1));
       _mov(Dest, T);
     }
@@ skipping 37 matching lines @@
   UnimplementedError(Func->getContext()->getFlags());
 }
 
 void TargetARM32::lowerFcmp(const InstFcmp *Inst) {
   (void)Inst;
   UnimplementedError(Func->getContext()->getFlags());
 }
 
 void TargetARM32::lowerIcmp(const InstIcmp *Inst) {
   Variable *Dest = Inst->getDest();
-  Operand *Src0 = Inst->getSrc(0);
-  Operand *Src1 = Inst->getSrc(1);
+  Operand *Src0 = legalizeUndef(Inst->getSrc(0));
+  Operand *Src1 = legalizeUndef(Inst->getSrc(1));
 
   if (isVectorType(Dest->getType())) {
     UnimplementedError(Func->getContext()->getFlags());
     return;
   }
 
   // a=icmp cond, b, c ==>
   // GCC does:
   //   cmp      b.hi, c.hi     or  cmp      b.lo, c.lo
   //   cmp.eq   b.lo, c.lo         sbcs t1, b.hi, c.hi
@@ skipping 148 matching lines @@
     return;
   case Intrinsics::AtomicStore: {
     UnimplementedError(Func->getContext()->getFlags());
     return;
   }
   case Intrinsics::Bswap: {
     Variable *Dest = Instr->getDest();
     Operand *Val = Instr->getArg(0);
     Type Ty = Val->getType();
     if (Ty == IceType_i64) {
+      Val = legalizeUndef(Val);
       Variable *Val_Lo = legalizeToVar(loOperand(Val));
       Variable *Val_Hi = legalizeToVar(hiOperand(Val));
       Variable *T_Lo = makeReg(IceType_i32);
       Variable *T_Hi = makeReg(IceType_i32);
       Variable *DestLo = llvm::cast<Variable>(loOperand(Dest));
       Variable *DestHi = llvm::cast<Variable>(hiOperand(Dest));
       _rev(T_Lo, Val_Lo);
       _rev(T_Hi, Val_Hi);
       _mov(DestLo, T_Hi);
       _mov(DestHi, T_Lo);
@@ skipping 32 matching lines @@
     }
     return;
   }
   case Intrinsics::Ctlz: {
     // The "is zero undef" parameter is ignored and we always return
     // a well-defined value.
     Operand *Val = Instr->getArg(0);
     Variable *ValLoR;
     Variable *ValHiR = nullptr;
     if (Val->getType() == IceType_i64) {
+      Val = legalizeUndef(Val);
       ValLoR = legalizeToVar(loOperand(Val));
       ValHiR = legalizeToVar(hiOperand(Val));
     } else {
       ValLoR = legalizeToVar(Val);
     }
     lowerCLZ(Instr->getDest(), ValLoR, ValHiR);
     return;
   }
   case Intrinsics::Cttz: {
     // Essentially like Clz, but reverse the bits first.
     Operand *Val = Instr->getArg(0);
     Variable *ValLoR;
     Variable *ValHiR = nullptr;
     if (Val->getType() == IceType_i64) {
+      Val = legalizeUndef(Val);
       ValLoR = legalizeToVar(loOperand(Val));
       ValHiR = legalizeToVar(hiOperand(Val));
       Variable *TLo = makeReg(IceType_i32);
       Variable *THi = makeReg(IceType_i32);
       _rbit(TLo, ValLoR);
       _rbit(THi, ValHiR);
       ValLoR = THi;
       ValHiR = TLo;
     } else {
       ValLoR = legalizeToVar(Val);
@@ skipping 146 matching lines @@
 
 void TargetARM32::lowerPhi(const InstPhi * /*Inst*/) {
   Func->setError("Phi found in regular instruction list");
 }
 
 void TargetARM32::lowerRet(const InstRet *Inst) {
   Variable *Reg = nullptr;
   if (Inst->hasRetValue()) {
     Operand *Src0 = Inst->getRetValue();
     if (Src0->getType() == IceType_i64) {
+      Src0 = legalizeUndef(Src0);
       Variable *R0 = legalizeToVar(loOperand(Src0), RegARM32::Reg_r0);
       Variable *R1 = legalizeToVar(hiOperand(Src0), RegARM32::Reg_r1);
       Reg = R0;
       Context.insert(InstFakeUse::create(Func, R1));
     } else if (isScalarFloatingType(Src0->getType())) {
       UnimplementedError(Func->getContext()->getFlags());
     } else if (isVectorType(Src0->getType())) {
       UnimplementedError(Func->getContext()->getFlags());
     } else {
       Operand *Src0F = legalize(Src0, Legal_Reg | Legal_Flex);
@@ skipping 30 matching lines @@
     UnimplementedError(Func->getContext()->getFlags());
     return;
   }
   // TODO(jvoung): handle folding opportunities.
   // cmp cond, #0; mov t, SrcF; mov_cond t, SrcT; mov dest, t
   Variable *CmpOpnd0 = legalizeToVar(Condition);
   Operand *CmpOpnd1 = Ctx->getConstantZero(IceType_i32);
   _cmp(CmpOpnd0, CmpOpnd1);
   CondARM32::Cond Cond = CondARM32::NE;
   if (DestTy == IceType_i64) {
+    SrcT = legalizeUndef(SrcT);
+    SrcF = legalizeUndef(SrcF);
     // Set the low portion.
     Variable *DestLo = llvm::cast<Variable>(loOperand(Dest));
     Variable *TLo = nullptr;
     Operand *SrcFLo = legalize(loOperand(SrcF), Legal_Reg | Legal_Flex);
     _mov(TLo, SrcFLo);
     Operand *SrcTLo = legalize(loOperand(SrcT), Legal_Reg | Legal_Flex);
     _mov_nonkillable(TLo, SrcTLo, Cond);
     _mov(DestLo, TLo);
     // Set the high portion.
     Variable *DestHi = llvm::cast<Variable>(hiOperand(Dest));
@@ skipping 13 matching lines @@
   _mov(Dest, T);
 }
 
 void TargetARM32::lowerStore(const InstStore *Inst) {
   Operand *Value = Inst->getData();
   Operand *Addr = Inst->getAddr();
   OperandARM32Mem *NewAddr = formMemoryOperand(Addr, Value->getType());
   Type Ty = NewAddr->getType();
 
   if (Ty == IceType_i64) {
+    Value = legalizeUndef(Value);
     Variable *ValueHi = legalizeToVar(hiOperand(Value));
     Variable *ValueLo = legalizeToVar(loOperand(Value));
     _str(ValueHi, llvm::cast<OperandARM32Mem>(hiOperand(NewAddr)));
     _str(ValueLo, llvm::cast<OperandARM32Mem>(loOperand(NewAddr)));
   } else if (isVectorType(Ty)) {
     UnimplementedError(Func->getContext()->getFlags());
   } else {
     Variable *ValueR = legalizeToVar(Value);
     _str(ValueR, NewAddr);
   }
 }
 
 void TargetARM32::doAddressOptStore() {
   UnimplementedError(Func->getContext()->getFlags());
 }
 
 void TargetARM32::lowerSwitch(const InstSwitch *Inst) {
   // This implements the most naive possible lowering.
   // cmp a,val[0]; jeq label[0]; cmp a,val[1]; jeq label[1]; ... jmp default
   Operand *Src0 = Inst->getComparison();
   SizeT NumCases = Inst->getNumCases();
   if (Src0->getType() == IceType_i64) {
-    // TODO(jvoung): handle and test undef for Src0
+    Src0 = legalizeUndef(Src0);
     Variable *Src0Lo = legalizeToVar(loOperand(Src0));
     Variable *Src0Hi = legalizeToVar(hiOperand(Src0));
     for (SizeT I = 0; I < NumCases; ++I) {
       Operand *ValueLo = Ctx->getConstantInt32(Inst->getValue(I));
       Operand *ValueHi = Ctx->getConstantInt32(Inst->getValue(I) >> 32);
       ValueLo = legalize(ValueLo, Legal_Reg | Legal_Flex);
       ValueHi = legalize(ValueHi, Legal_Reg | Legal_Flex);
       _cmp(Src0Lo, ValueLo);
       _cmp(Src0Hi, ValueHi, CondARM32::EQ);
       _br(Inst->getLabel(I), CondARM32::EQ);
@@ skipping 50 matching lines @@
   } else {
     // Mov's Src operand can really only be the flexible second operand type
     // or a register. Users should guarantee that.
     _mov(Reg, Src);
   }
   return Reg;
 }
 
 Operand *TargetARM32::legalize(Operand *From, LegalMask Allowed,
                                int32_t RegNum) {
+  Type Ty = From->getType();
   // Assert that a physical register is allowed.  To date, all calls
   // to legalize() allow a physical register. Legal_Flex converts
   // registers to the right type OperandARM32FlexReg as needed.
   assert(Allowed & Legal_Reg);
   // Go through the various types of operands:
   // OperandARM32Mem, OperandARM32Flex, Constant, and Variable.
   // Given the above assertion, if type of operand is not legal
   // (e.g., OperandARM32Mem and !Legal_Mem), we can always copy
   // to a register.
   if (auto Mem = llvm::dyn_cast<OperandARM32Mem>(From)) {
     // Before doing anything with a Mem operand, we need to ensure
     // that the Base and Index components are in physical registers.
     Variable *Base = Mem->getBase();
     Variable *Index = Mem->getIndex();
     Variable *RegBase = nullptr;
     Variable *RegIndex = nullptr;
     if (Base) {
       RegBase = legalizeToVar(Base);
     }
     if (Index) {
       RegIndex = legalizeToVar(Index);
     }
     // Create a new operand if there was a change.
     if (Base != RegBase || Index != RegIndex) {
       // There is only a reg +/- reg or reg + imm form.
       // Figure out which to re-create.
       if (Mem->isRegReg()) {
-        Mem = OperandARM32Mem::create(Func, Mem->getType(), RegBase, RegIndex,
+        Mem = OperandARM32Mem::create(Func, Ty, RegBase, RegIndex,
                                       Mem->getShiftOp(), Mem->getShiftAmt(),
                                       Mem->getAddrMode());
       } else {
-        Mem = OperandARM32Mem::create(Func, Mem->getType(), RegBase,
-                                      Mem->getOffset(), Mem->getAddrMode());
+        Mem = OperandARM32Mem::create(Func, Ty, RegBase, Mem->getOffset(),
+                                      Mem->getAddrMode());
       }
     }
     if (!(Allowed & Legal_Mem)) {
-      Type Ty = Mem->getType();
       Variable *Reg = makeReg(Ty, RegNum);
       _ldr(Reg, Mem);
       From = Reg;
     } else {
       From = Mem;
     }
     return From;
   }
 
   if (auto Flex = llvm::dyn_cast<OperandARM32Flex>(From)) {
     if (!(Allowed & Legal_Flex)) {
       if (auto FlexReg = llvm::dyn_cast<OperandARM32FlexReg>(Flex)) {
         if (FlexReg->getShiftOp() == OperandARM32::kNoShift) {
           From = FlexReg->getReg();
           // Fall through and let From be checked as a Variable below,
           // where it may or may not need a register.
         } else {
           return copyToReg(Flex, RegNum);
         }
       } else {
         return copyToReg(Flex, RegNum);
       }
     } else {
       return From;
     }
   }
 
   if (llvm::isa<Constant>(From)) {
     if (llvm::isa<ConstantUndef>(From)) {
-      // Lower undefs to zero.  Another option is to lower undefs to an
-      // uninitialized register; however, using an uninitialized register
-      // results in less predictable code.
-      if (isVectorType(From->getType()))
-        return makeVectorOfZeros(From->getType(), RegNum);
-      From = Ctx->getConstantZero(From->getType());
+      From = legalizeUndef(From, RegNum);
+      if (isVectorType(Ty))
+        return From;
     }
     // There should be no constants of vector type (other than undef).
-    assert(!isVectorType(From->getType()));
+    assert(!isVectorType(Ty));
     bool CanBeFlex = Allowed & Legal_Flex;
-    if (auto C32 = llvm::dyn_cast<ConstantInteger32>(From)) {
+    if (auto *C32 = llvm::dyn_cast<ConstantInteger32>(From)) {
       uint32_t RotateAmt;
       uint32_t Immed_8;
       uint32_t Value = static_cast<uint32_t>(C32->getValue());
       // Check if the immediate will fit in a Flexible second operand,
       // if a Flexible second operand is allowed. We need to know the exact
       // value, so that rules out relocatable constants.
       // Also try the inverse and use MVN if possible.
       if (CanBeFlex &&
           OperandARM32FlexImm::canHoldImm(Value, &RotateAmt, &Immed_8)) {
-        return OperandARM32FlexImm::create(Func, From->getType(), Immed_8,
-                                           RotateAmt);
+        return OperandARM32FlexImm::create(Func, Ty, Immed_8, RotateAmt);
       } else if (CanBeFlex && OperandARM32FlexImm::canHoldImm(
                                   ~Value, &RotateAmt, &Immed_8)) {
-        auto InvertedFlex = OperandARM32FlexImm::create(Func, From->getType(),
-                                                        Immed_8, RotateAmt);
-        Type Ty = From->getType();
+        auto InvertedFlex =
+            OperandARM32FlexImm::create(Func, Ty, Immed_8, RotateAmt);
         Variable *Reg = makeReg(Ty, RegNum);
         _mvn(Reg, InvertedFlex);
         return Reg;
       } else {
         // Do a movw/movt to a register.
-        Type Ty = From->getType();
         Variable *Reg = makeReg(Ty, RegNum);
         uint32_t UpperBits = (Value >> 16) & 0xFFFF;
         _movw(Reg,
               UpperBits != 0 ? Ctx->getConstantInt32(Value & 0xFFFF) : C32);
         if (UpperBits != 0) {
           _movt(Reg, Ctx->getConstantInt32(UpperBits));
         }
         return Reg;
       }
-    } else if (auto C = llvm::dyn_cast<ConstantRelocatable>(From)) {
-      Type Ty = From->getType();
+    } else if (auto *C = llvm::dyn_cast<ConstantRelocatable>(From)) {
       Variable *Reg = makeReg(Ty, RegNum);
       _movw(Reg, C);
       _movt(Reg, C);
       return Reg;
     } else {
       // Load floats/doubles from literal pool.
       UnimplementedError(Func->getContext()->getFlags());
       From = copyToReg(From, RegNum);
     }
     return From;
@@ skipping 12 matching lines @@
         (RegNum != Variable::NoRegister && RegNum != Var->getRegNum())) {
       From = copyToReg(From, RegNum);
     }
     return From;
   }
   llvm_unreachable("Unhandled operand kind in legalize()");
 
   return From;
 }
 
-// Provide a trivial wrapper to legalize() for this common usage.
+/// Provide a trivial wrapper to legalize() for this common usage.
 Variable *TargetARM32::legalizeToVar(Operand *From, int32_t RegNum) {
   return llvm::cast<Variable>(legalize(From, Legal_Reg, RegNum));
 }
 
+/// Legalize undef values to concrete values.
+Operand *TargetARM32::legalizeUndef(Operand *From, int32_t RegNum) {
+  Type Ty = From->getType();
+  if (llvm::isa<ConstantUndef>(From)) {
+    // Lower undefs to zero.  Another option is to lower undefs to an
+    // uninitialized register; however, using an uninitialized register
+    // results in less predictable code.
+    //
+    // If in the future the implementation is changed to lower undef
+    // values to uninitialized registers, a FakeDef will be needed:
+    //     Context.insert(InstFakeDef::create(Func, Reg));
+    // This is in order to ensure that the live range of Reg is not
+    // overestimated.  If the constant being lowered is a 64 bit value,
+    // then the result should be split and the lo and hi components will
+    // need to go in uninitialized registers.
+    if (isVectorType(Ty))
+      return makeVectorOfZeros(Ty, RegNum);
+    return Ctx->getConstantZero(Ty);
+  }
+  return From;
+}
+
 OperandARM32Mem *TargetARM32::formMemoryOperand(Operand *Operand, Type Ty) {
   OperandARM32Mem *Mem = llvm::dyn_cast<OperandARM32Mem>(Operand);
   // It may be the case that address mode optimization already creates
   // an OperandARM32Mem, so in that case it wouldn't need another level
   // of transformation.
   if (Mem) {
     return llvm::cast<OperandARM32Mem>(legalize(Mem));
   }
   // If we didn't do address mode optimization, then we only
   // have a base/offset to work with. ARM always requires a base
@@ skipping 142 matching lines @@
       << ".eabi_attribute 68, 1   @ Tag_Virtualization_use\n";
   if (CPUFeatures.hasFeature(TargetARM32Features::HWDivArm)) {
     Str << ".eabi_attribute 44, 2   @ Tag_DIV_use\n";
   }
   // Technically R9 is used for TLS with Sandboxing, and we reserve it.
   // However, for compatibility with current NaCl LLVM, don't claim that.
   Str << ".eabi_attribute 14, 3   @ Tag_ABI_PCS_R9_use: Not used\n";
 }
 
 } // end of namespace Ice