PPC: Remove unused jump_elimination_allowed parameter to Assembler::branch_offset().

src/ppc/assembler-ppc.h

 // Copyright (c) 1994-2006 Sun Microsystems Inc.
 // All Rights Reserved.
 //
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions
 // are met:
 //
 // - Redistributions of source code must retain the above copyright notice,
 // this list of conditions and the following disclaimer.
 //
@@ skipping 573 matching lines @@
   // bound position.  If already linked, returns the position of the prior link.
   // Otherwise, returns the current pc_offset().
   int link(Label* L);
 
   // Determines if Label is bound and near enough so that a single
   // branch instruction can be used to reach it.
   bool is_near(Label* L, Condition cond);
 
   // Returns the branch offset to the given label from the current code position
   // Links the label to the current position if it is still unbound
-  // Manages the jump elimination optimization if the second parameter is true.
-  int branch_offset(Label* L, bool jump_elimination_allowed) {
+  int branch_offset(Label* L) {
     int position = link(L);
     return position - pc_offset();
   }
 
   // Puts a labels target address at the given position.
   // The high 8 bits are set to zero.
   void label_at_put(Label* L, int at_offset);
 
   INLINE(static bool IsConstantPoolLoadStart(
       Address pc, ConstantPoolEntry::Access* access = nullptr));
@@ skipping 140 matching lines @@
   void bclr(BOfield bo, LKBit lk);
   void blr();
   void bc(int branch_offset, BOfield bo, int condition_bit, LKBit lk = LeaveLK);
   void b(int branch_offset, LKBit lk);
 
   void bcctr(BOfield bo, LKBit lk);
   void bctr();
   void bctrl();
 
   // Convenience branch instructions using labels
-  void b(Label* L, LKBit lk = LeaveLK) { b(branch_offset(L, false), lk); }
+  void b(Label* L, LKBit lk = LeaveLK) { b(branch_offset(L), lk); }
 
   inline CRegister cmpi_optimization(CRegister cr) {
     // Check whether the branch is preceeded by an optimizable cmpi against 0.
     // The cmpi can be deleted if it is also preceeded by an instruction that
     // sets the register used by the compare and supports a dot form.
     unsigned int sradi_mask = kOpcodeMask | kExt2OpcodeVariant2Mask;
     unsigned int srawi_mask = kOpcodeMask | kExt2OpcodeMask;
     int pos = pc_offset();
     int cmpi_pos = pc_offset() - kInstrSize;
 
@@ skipping 24 matching lines @@
     return cr;
   }
 
   void bc_short(Condition cond, Label* L, CRegister cr = cr7,
                 LKBit lk = LeaveLK) {
     DCHECK(cond != al);
     DCHECK(cr.code() >= 0 && cr.code() <= 7);
 
     cr = cmpi_optimization(cr);
 
-    int b_offset = branch_offset(L, false);
+    int b_offset = branch_offset(L);
 
     switch (cond) {
       case eq:
         bc(b_offset, BT, encode_crbit(cr, CR_EQ), lk);
         break;
       case ne:
         bc(b_offset, BF, encode_crbit(cr, CR_EQ), lk);
         break;
       case gt:
         bc(b_offset, BT, encode_crbit(cr, CR_GT), lk);
@@ skipping 112 matching lines @@
   }
   void boverflow(Label* L, CRegister cr = cr0, LKBit lk = LeaveLK) {
     b(overflow, L, cr, lk);
   }
   void bnooverflow(Label* L, CRegister cr = cr0, LKBit lk = LeaveLK) {
     b(nooverflow, L, cr, lk);
   }
 
   // Decrement CTR; branch if CTR != 0
   void bdnz(Label* L, LKBit lk = LeaveLK) {
-    bc(branch_offset(L, false), DCBNZ, 0, lk);
+    bc(branch_offset(L), DCBNZ, 0, lk);
   }
 
   // Data-processing instructions
 
   void sub(Register dst, Register src1, Register src2, OEBit s = LeaveOE,
            RCBit r = LeaveRC);
 
   void subfic(Register dst, Register src, const Operand& imm);
 
   void subfc(Register dst, Register src1, Register src2, OEBit s = LeaveOE,
@@ skipping 636 matching lines @@
 
 
 class EnsureSpace BASE_EMBEDDED {
  public:
   explicit EnsureSpace(Assembler* assembler) { assembler->CheckBuffer(); }
 };
 }
 }  // namespace v8::internal
 
 #endif  // V8_PPC_ASSEMBLER_PPC_H_