Subzero: Fix register encodings.

src/IceInstX8632.def

 //===- subzero/src/IceInstX8632.def - X-macros for x86-32 insts -*- C++ -*-===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file defines properties of lowered x86-32 instructions in the
 // form of x-macros.
 //
 //===----------------------------------------------------------------------===//
 
 #ifndef SUBZERO_SRC_ICEINSTX8632_DEF
 #define SUBZERO_SRC_ICEINSTX8632_DEF
 
 // NOTE: esp is not considered isInt, to avoid register allocating it.
 #define REGX8632_GPR_TABLE                                              \
   /* val, encode, name, name16, name8, scratch, preserved, stackptr,    \
      frameptr, isI8, isInt, isFP */                                     \
-  X(Reg_eax, = 0,             "eax",  "ax", "al", 1, 0, 0, 0, 1, 1, 0)  \
-  X(Reg_ecx, = Reg_eax + 1,   "ecx",  "cx", "cl", 1, 0, 0, 0, 1, 1, 0)  \
-  X(Reg_edx, = Reg_eax + 2,   "edx",  "dx", "dl", 1, 0, 0, 0, 1, 1, 0)  \
-  X(Reg_ebx, = Reg_eax + 3,   "ebx",  "bx", "bl", 0, 1, 0, 0, 1, 1, 0)  \
-  X(Reg_esp, = Reg_eax + 4,   "esp",  "sp", ""  , 0, 0, 1, 0, 0, 0, 0)  \
-  X(Reg_ebp, = Reg_eax + 5,   "ebp",  "bp", ""  , 0, 1, 0, 1, 0, 1, 0)  \
-  X(Reg_esi, = Reg_eax + 6,   "esi",  "si", ""  , 0, 1, 0, 0, 0, 1, 0)  \
-  X(Reg_edi, = Reg_eax + 7,   "edi",  "di", ""  , 0, 1, 0, 0, 0, 1, 0)
+  X(Reg_eax, 0, "eax", "ax", "al", 1, 0, 0, 0, 1, 1, 0)                 \
+  X(Reg_ecx, 1, "ecx", "cx", "cl", 1, 0, 0, 0, 1, 1, 0)                 \
+  X(Reg_edx, 2, "edx", "dx", "dl", 1, 0, 0, 0, 1, 1, 0)                 \
+  X(Reg_ebx, 3, "ebx", "bx", "bl", 0, 1, 0, 0, 1, 1, 0)                 \
+  X(Reg_esp, 4, "esp", "sp", ""  , 0, 0, 1, 0, 0, 0, 0)                 \
+  X(Reg_ebp, 5, "ebp", "bp", ""  , 0, 1, 0, 1, 0, 1, 0)                 \
+  X(Reg_esi, 6, "esi", "si", ""  , 0, 1, 0, 0, 0, 1, 0)                 \
+  X(Reg_edi, 7, "edi", "di", ""  , 0, 1, 0, 0, 0, 1, 0)      
 
 #define REGX8632_XMM_TABLE                                              \
-  X(Reg_xmm0, = 0,            "xmm0", ""  , ""  , 1, 0, 0, 0, 0, 0, 1)  \
-  X(Reg_xmm1, = Reg_xmm0 + 1, "xmm1", ""  , ""  , 1, 0, 0, 0, 0, 0, 1)  \
-  X(Reg_xmm2, = Reg_xmm0 + 2, "xmm2", ""  , ""  , 1, 0, 0, 0, 0, 0, 1)  \
-  X(Reg_xmm3, = Reg_xmm0 + 3, "xmm3", ""  , ""  , 1, 0, 0, 0, 0, 0, 1)  \
-  X(Reg_xmm4, = Reg_xmm0 + 4, "xmm4", ""  , ""  , 1, 0, 0, 0, 0, 0, 1)  \
-  X(Reg_xmm5, = Reg_xmm0 + 5, "xmm5", ""  , ""  , 1, 0, 0, 0, 0, 0, 1)  \
-  X(Reg_xmm6, = Reg_xmm0 + 6, "xmm6", ""  , ""  , 1, 0, 0, 0, 0, 0, 1)  \
-  X(Reg_xmm7, = Reg_xmm0 + 7, "xmm7", ""  , ""  , 1, 0, 0, 0, 0, 0, 1)  \
+  X(Reg_xmm0, 0, "xmm0", "" , "" , 1, 0, 0, 0, 0, 0, 1)                 \
+  X(Reg_xmm1, 1, "xmm1", "" , "" , 1, 0, 0, 0, 0, 0, 1)                 \
+  X(Reg_xmm2, 2, "xmm2", "" , "" , 1, 0, 0, 0, 0, 0, 1)                 \
+  X(Reg_xmm3, 3, "xmm3", "" , "" , 1, 0, 0, 0, 0, 0, 1)                 \
+  X(Reg_xmm4, 4, "xmm4", "" , "" , 1, 0, 0, 0, 0, 0, 1)                 \
+  X(Reg_xmm5, 5, "xmm5", "" , "" , 1, 0, 0, 0, 0, 0, 1)                 \
+  X(Reg_xmm6, 6, "xmm6", "" , "" , 1, 0, 0, 0, 0, 0, 1)                 \
+  X(Reg_xmm7, 7, "xmm7", "" , "" , 1, 0, 0, 0, 0, 0, 1)                 \
 //#define X(val, encode, name, name16, name8, scratch, preserved, stackptr,
 //          frameptr, isI8, isInt, isFP)
 
 // We also provide a combined table, so that there is a namespace where
 // all of the registers are considered and have distinct numberings.
 // This is in contrast to the above, where the "encode" is based on how
 // the register numbers will be encoded in binaries and values can overlap.
 // Note that the isI8 attributed of Reg_ah is not set.  In general we
 // don't want the register allocator choosing Reg_ah, in particular
 // for lowering insertelement to pinsrb where internally we use an
 // 8-bit operand but externally pinsrb uses a 32-bit register, in
 // which Reg_ah doesn't map to eax.
 #define REGX8632_TABLE                                                  \
   /* val, encode, name, name16, name8, scratch, preserved, stackptr,    \
      frameptr, isI8, isInt, isFP */                                     \
   REGX8632_GPR_TABLE                                                    \
-  X(Reg_ah,  = Reg_eax + 4,   "???",  ""  , "ah", 0, 0, 0, 0, 0, 0, 0)  \
+  X(Reg_ah, 4, "???", "" , "ah", 0, 0, 0, 0, 0, 0, 0)                   \
   REGX8632_XMM_TABLE
 //#define X(val, encode, name, name16, name8, scratch, preserved, stackptr,
 //          frameptr, isI8, isInt, isFP)
 
 #define REGX8632_TABLE_BOUNDS                                           \
   /* val, init */                                                       \
   X(Reg_GPR_First, = Reg_eax)                                           \
   X(Reg_GPR_Last,  = Reg_edi)                                           \
   X(Reg_XMM_First, = Reg_xmm0)                                          \
   X(Reg_XMM_Last,  = Reg_xmm7)                                          \
@@ skipping 81 matching lines @@
   X(IceType_v4i1,  IceType_i32 , "?" , ""  , "d",  "",  "")      \
   X(IceType_v8i1,  IceType_i16 , "?" , ""  , "w",  "",  "")      \
   X(IceType_v16i1, IceType_i8  , "?" , ""  , "b",  "",  "")      \
   X(IceType_v16i8, IceType_i8  , "?" , ""  , "b",  "",  "")      \
   X(IceType_v8i16, IceType_i16 , "?" , ""  , "w",  "",  "")      \
   X(IceType_v4i32, IceType_i32 , "dq", ""  , "d",  "",  "")      \
   X(IceType_v4f32, IceType_f32 , "ps", ""  , "d",  "",  "")      \
 //#define X(tag, elementty, cvt, sdss, pack, width, fld)
 
 #endif // SUBZERO_SRC_ICEINSTX8632_DEF