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1 // Copyright (c) 1994-2006 Sun Microsystems Inc. | 1 // Copyright (c) 1994-2006 Sun Microsystems Inc. |
2 // All Rights Reserved. | 2 // All Rights Reserved. |
3 // | 3 // |
4 // Redistribution and use in source and binary forms, with or without | 4 // Redistribution and use in source and binary forms, with or without |
5 // modification, are permitted provided that the following conditions | 5 // modification, are permitted provided that the following conditions |
6 // are met: | 6 // are met: |
7 // | 7 // |
8 // - Redistributions of source code must retain the above copyright notice, | 8 // - Redistributions of source code must retain the above copyright notice, |
9 // this list of conditions and the following disclaimer. | 9 // this list of conditions and the following disclaimer. |
10 // | 10 // |
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2529 dst.split_code(&vd, &d); | 2529 dst.split_code(&vd, &d); |
2530 int vn, n; | 2530 int vn, n; |
2531 src1.split_code(&vn, &n); | 2531 src1.split_code(&vn, &n); |
2532 int vm, m; | 2532 int vm, m; |
2533 src2.split_code(&vm, &m); | 2533 src2.split_code(&vm, &m); |
2534 emit(cond | 0x1C*B23 | d*B22 | vn*B16 | vd*B12 | 0x5*B9 | B8 | n*B7 | m*B5 | | 2534 emit(cond | 0x1C*B23 | d*B22 | vn*B16 | vd*B12 | 0x5*B9 | B8 | n*B7 | m*B5 | |
2535 vm); | 2535 vm); |
2536 } | 2536 } |
2537 | 2537 |
2538 | 2538 |
| 2539 void Assembler::vmls(const DwVfpRegister dst, |
| 2540 const DwVfpRegister src1, |
| 2541 const DwVfpRegister src2, |
| 2542 const Condition cond) { |
| 2543 // Instruction details available in ARM DDI 0406C.b, A8-932. |
| 2544 // cond(31-28) | 11100(27-23) | D(22) | 00(21-20) | Vn(19-16) | |
| 2545 // Vd(15-12) | 101(11-9) | sz=1(8) | N(7) | op=1(6) | M(5) | 0(4) | Vm(3-0) |
| 2546 int vd, d; |
| 2547 dst.split_code(&vd, &d); |
| 2548 int vn, n; |
| 2549 src1.split_code(&vn, &n); |
| 2550 int vm, m; |
| 2551 src2.split_code(&vm, &m); |
| 2552 emit(cond | 0x1C*B23 | d*B22 | vn*B16 | vd*B12 | 0x5*B9 | B8 | n*B7 | B6 | |
| 2553 m*B5 | vm); |
| 2554 } |
| 2555 |
| 2556 |
2539 void Assembler::vdiv(const DwVfpRegister dst, | 2557 void Assembler::vdiv(const DwVfpRegister dst, |
2540 const DwVfpRegister src1, | 2558 const DwVfpRegister src1, |
2541 const DwVfpRegister src2, | 2559 const DwVfpRegister src2, |
2542 const Condition cond) { | 2560 const Condition cond) { |
2543 // Dd = vdiv(Dn, Dm) double precision floating point division. | 2561 // Dd = vdiv(Dn, Dm) double precision floating point division. |
2544 // Dd = D:Vd; Dm=M:Vm; Dn=N:Vm. | 2562 // Dd = D:Vd; Dm=M:Vm; Dn=N:Vm. |
2545 // Instruction details available in ARM DDI 0406C.b, A8-882. | 2563 // Instruction details available in ARM DDI 0406C.b, A8-882. |
2546 // cond(31-28) | 11101(27-23)| D(22) | 00(21-20) | Vn(19-16) | | 2564 // cond(31-28) | 11101(27-23)| D(22) | 00(21-20) | Vn(19-16) | |
2547 // Vd(15-12) | 101(11-9) | sz=1(8) | N(7) | 0(6) | M(5) | 0(4) | Vm(3-0) | 2565 // Vd(15-12) | 101(11-9) | sz=1(8) | N(7) | 0(6) | M(5) | 0(4) | Vm(3-0) |
2548 ASSERT(CpuFeatures::IsEnabled(VFP2)); | 2566 ASSERT(CpuFeatures::IsEnabled(VFP2)); |
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3025 | 3043 |
3026 // Since a constant pool was just emitted, move the check offset forward by | 3044 // Since a constant pool was just emitted, move the check offset forward by |
3027 // the standard interval. | 3045 // the standard interval. |
3028 next_buffer_check_ = pc_offset() + kCheckPoolInterval; | 3046 next_buffer_check_ = pc_offset() + kCheckPoolInterval; |
3029 } | 3047 } |
3030 | 3048 |
3031 | 3049 |
3032 } } // namespace v8::internal | 3050 } } // namespace v8::internal |
3033 | 3051 |
3034 #endif // V8_TARGET_ARCH_ARM | 3052 #endif // V8_TARGET_ARCH_ARM |
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