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Issue 1227733002: VM: Load common VM constants from Thread on ARM and MIPS. (Closed) Base URL: git@github.com:dart-lang/sdk.git@master
Patch Set: Created 5 years, 5 months ago
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1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file 1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file
2 // for details. All rights reserved. Use of this source code is governed by a 2 // for details. All rights reserved. Use of this source code is governed by a
3 // BSD-style license that can be found in the LICENSE file. 3 // BSD-style license that can be found in the LICENSE file.
4 4
5 #include "vm/globals.h" // NOLINT 5 #include "vm/globals.h" // NOLINT
6 #if defined(TARGET_ARCH_ARM) 6 #if defined(TARGET_ARCH_ARM)
7 7
8 #include "vm/assembler.h" 8 #include "vm/assembler.h"
9 #include "vm/cpu.h" 9 #include "vm/cpu.h"
10 #include "vm/longjump.h" 10 #include "vm/longjump.h"
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1560 1560
1561 void Assembler::LoadIsolate(Register rd) { 1561 void Assembler::LoadIsolate(Register rd) {
1562 ldr(rd, Address(THR, Thread::isolate_offset())); 1562 ldr(rd, Address(THR, Thread::isolate_offset()));
1563 } 1563 }
1564 1564
1565 1565
1566 void Assembler::LoadObjectHelper(Register rd, 1566 void Assembler::LoadObjectHelper(Register rd,
1567 const Object& object, 1567 const Object& object,
1568 Condition cond, 1568 Condition cond,
1569 bool is_unique) { 1569 bool is_unique) {
1570 // Load common VM constants from the thread. This works also in places where
1571 // no constant pool is set up (e.g. intrinsic code).
1572 if (Thread::CanLoadFromThread(object)) {
1573 ldr(rd, Address(THR, Thread::OffsetFromThread(object)), cond);
1574 return;
1575 }
1570 // Smis and VM heap objects are never relocated; do not use object pool. 1576 // Smis and VM heap objects are never relocated; do not use object pool.
1571 if (object.IsSmi()) { 1577 if (object.IsSmi()) {
1572 LoadImmediate(rd, reinterpret_cast<int32_t>(object.raw()), cond); 1578 LoadImmediate(rd, reinterpret_cast<int32_t>(object.raw()), cond);
1573 } else if (object.InVMHeap() || !allow_constant_pool()) { 1579 } else if (object.InVMHeap() || !allow_constant_pool()) {
1574 // Make sure that class CallPattern is able to decode this load immediate. 1580 // Make sure that class CallPattern is able to decode this load immediate.
1575 const int32_t object_raw = reinterpret_cast<int32_t>(object.raw()); 1581 const int32_t object_raw = reinterpret_cast<int32_t>(object.raw());
1576 LoadImmediate(rd, object_raw, cond); 1582 LoadImmediate(rd, object_raw, cond);
1577 } else { 1583 } else {
1578 // Make sure that class CallPattern is able to decode this load from the 1584 // Make sure that class CallPattern is able to decode this load from the
1579 // object pool. 1585 // object pool.
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1801 } 1807 }
1802 // A store buffer update is required. 1808 // A store buffer update is required.
1803 RegList regs = (1 << LR); 1809 RegList regs = (1 << LR);
1804 if (value != R0) { 1810 if (value != R0) {
1805 regs |= (1 << R0); // Preserve R0. 1811 regs |= (1 << R0); // Preserve R0.
1806 } 1812 }
1807 PushList(regs); 1813 PushList(regs);
1808 if (object != R0) { 1814 if (object != R0) {
1809 mov(R0, Operand(object)); 1815 mov(R0, Operand(object));
1810 } 1816 }
1811 StubCode* stub_code = Isolate::Current()->stub_code(); 1817 ldr(LR, Address(THR, Thread::update_store_buffer_entry_point_offset()));
1812 BranchLink(&stub_code->UpdateStoreBufferLabel()); 1818 blx(LR);
1813 PopList(regs); 1819 PopList(regs);
1814 Bind(&done); 1820 Bind(&done);
1815 } 1821 }
1816 1822
1817 1823
1818 void Assembler::StoreIntoObjectOffset(Register object, 1824 void Assembler::StoreIntoObjectOffset(Register object,
1819 int32_t offset, 1825 int32_t offset,
1820 Register value, 1826 Register value,
1821 bool can_value_be_smi) { 1827 bool can_value_be_smi) {
1822 int32_t ignored = 0; 1828 int32_t ignored = 0;
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3603 3609
3604 3610
3605 const char* Assembler::FpuRegisterName(FpuRegister reg) { 3611 const char* Assembler::FpuRegisterName(FpuRegister reg) {
3606 ASSERT((0 <= reg) && (reg < kNumberOfFpuRegisters)); 3612 ASSERT((0 <= reg) && (reg < kNumberOfFpuRegisters));
3607 return fpu_reg_names[reg]; 3613 return fpu_reg_names[reg];
3608 } 3614 }
3609 3615
3610 } // namespace dart 3616 } // namespace dart
3611 3617
3612 #endif // defined TARGET_ARCH_ARM 3618 #endif // defined TARGET_ARCH_ARM
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