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Unified Diff: src/IceTargetLoweringX8664Traits.h

Issue 1224173006: Adds the x86-64 assembler. (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master
Patch Set: make format Created 5 years, 5 months ago
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« src/IceTargetLoweringX8664.def ('K') | « src/IceTargetLoweringX8664.def ('k') | unittest/IceAssemblerX8632Test.cpp » ('j') | unittest/IceAssemblerX8664Test.cpp » ('J')
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Index: src/IceTargetLoweringX8664Traits.h
diff --git a/src/IceTargetLoweringX8632Traits.h b/src/IceTargetLoweringX8664Traits.h
similarity index 83%
copy from src/IceTargetLoweringX8632Traits.h
copy to src/IceTargetLoweringX8664Traits.h
index ca15ea525daf55d5153a02c5843c803128fb2194..7133be13ae996f331d1c2135ead510877f8a4f92 100644
--- a/src/IceTargetLoweringX8632Traits.h
+++ b/src/IceTargetLoweringX8664Traits.h
@@ -1,4 +1,4 @@
-//===- subzero/src/IceTargetLoweringX8632Traits.h - x86-32 traits -*- C++ -*-=//
+//===- subzero/src/IceTargetLoweringX8664Traits.h - x86-64 traits -*- C++ -*-=//
//
// The Subzero Code Generator
//
@@ -8,38 +8,37 @@
//===----------------------------------------------------------------------===//
///
/// \file
-/// This file declares the X8632 Target Lowering Traits.
+/// This file declares the X8664 Target Lowering Traits.
///
//===----------------------------------------------------------------------===//
-#ifndef SUBZERO_SRC_ICETARGETLOWERINGX8632TRAITS_H
-#define SUBZERO_SRC_ICETARGETLOWERINGX8632TRAITS_H
+#ifndef SUBZERO_SRC_ICETARGETLOWERINGX8664TRAITS_H
+#define SUBZERO_SRC_ICETARGETLOWERINGX8664TRAITS_H
#include "IceAssembler.h"
-#include "IceConditionCodesX8632.h"
+#include "IceConditionCodesX8664.h"
#include "IceDefs.h"
#include "IceInst.h"
-#include "IceInstX8632.def"
+#include "IceInstX8664.def"
#include "IceOperand.h"
-#include "IceRegistersX8632.h"
-#include "IceTargetLoweringX8632.def"
+#include "IceRegistersX8664.h"
+#include "IceTargetLoweringX8664.def"
#include "IceTargetLowering.h"
namespace Ice {
-class TargetX8632;
+class TargetX8664;
-namespace X8632 {
-class AssemblerX8632;
-} // end of namespace X8632
+namespace X8664 {
+class AssemblerX8664;
+} // end of namespace X8664
namespace X86Internal {
template <class Machine> struct Insts;
template <class Machine> struct MachineTraits;
-template <class Machine> class TargetX86Base;
-template <> struct MachineTraits<TargetX8632> {
+template <> struct MachineTraits<TargetX8664> {
//----------------------------------------------------------------------------
// ______ ______ __ __
// /\ __ \/\ ___\/\ "-./ \
@@ -48,38 +47,58 @@ template <> struct MachineTraits<TargetX8632> {
// \/_/\/_/\/_____/\/_/ \/_/
//
//----------------------------------------------------------------------------
+ static constexpr bool Is64Bit = true;
+ static constexpr bool HasPopa = false;
+ static constexpr bool HasPusha = false;
+ static constexpr bool UsesX87 = false;
+ static constexpr ::Ice::RegX8664::GPRRegister Last8BitGPR =
+ ::Ice::RegX8664::GPRRegister::Encoded_Reg_r15d;
+
enum ScaleFactor { TIMES_1 = 0, TIMES_2 = 1, TIMES_4 = 2, TIMES_8 = 3 };
- using GPRRegister = ::Ice::RegX8632::GPRRegister;
- using XmmRegister = ::Ice::RegX8632::XmmRegister;
- using ByteRegister = ::Ice::RegX8632::ByteRegister;
- using X87STRegister = ::Ice::RegX8632::X87STRegister;
+ using GPRRegister = ::Ice::RegX8664::GPRRegister;
+ using XmmRegister = ::Ice::RegX8664::XmmRegister;
+ using ByteRegister = ::Ice::RegX8664::ByteRegister;
- using Cond = ::Ice::CondX86;
+ using Cond = ::Ice::CondX8664;
- using RegisterSet = ::Ice::RegX8632;
- static const GPRRegister Encoded_Reg_Accumulator = RegX8632::Encoded_Reg_eax;
- static const GPRRegister Encoded_Reg_Counter = RegX8632::Encoded_Reg_ecx;
- static const FixupKind PcRelFixup = llvm::ELF::R_386_PC32;
+ using RegisterSet = ::Ice::RegX8664;
+ static const GPRRegister Encoded_Reg_Accumulator = RegX8664::Encoded_Reg_eax;
+ static const GPRRegister Encoded_Reg_Counter = RegX8664::Encoded_Reg_ecx;
+ static const FixupKind PcRelFixup = llvm::ELF::R_386_PC32; // TODO(jpp): ???
class Operand {
public:
+ enum RexBits {
+ RexNone = 0x00,
+ RexBase = 0x40,
+ RexW = RexBase | (1 << 3),
+ RexR = RexBase | (1 << 2),
+ RexX = RexBase | (1 << 1),
+ RexB = RexBase | (1 << 0),
+ };
+
Operand(const Operand &other)
- : fixup_(other.fixup_), length_(other.length_) {
+ : fixup_(other.fixup_), rex_(other.rex_), length_(other.length_) {
memmove(&encoding_[0], &other.encoding_[0], other.length_);
}
Operand &operator=(const Operand &other) {
length_ = other.length_;
fixup_ = other.fixup_;
+ rex_ = other.rex_;
memmove(&encoding_[0], &other.encoding_[0], other.length_);
return *this;
}
uint8_t mod() const { return (encoding_at(0) >> 6) & 3; }
+ uint8_t rexX() const { return (rex_ & RexX) != RexX ? RexNone : RexX; }
+ uint8_t rexB() const { return (rex_ & RexB) != RexB ? RexNone : RexB; }
+
GPRRegister rm() const {
- return static_cast<GPRRegister>(encoding_at(0) & 7);
+ return static_cast<GPRRegister>((rexB() != 0 ? 0x08 : 0) |
+ (encoding_at(0) & 7));
}
ScaleFactor scale() const {
@@ -87,11 +106,13 @@ template <> struct MachineTraits<TargetX8632> {
}
GPRRegister index() const {
- return static_cast<GPRRegister>((encoding_at(1) >> 3) & 7);
+ return static_cast<GPRRegister>((rexX() != 0 ? 0x08 : 0) |
+ ((encoding_at(1) >> 3) & 7));
}
GPRRegister base() const {
- return static_cast<GPRRegister>(encoding_at(1) & 7);
+ return static_cast<GPRRegister>((rexB() != 0 ? 0x08 : 0) |
+ (encoding_at(1) & 7));
}
int8_t disp8() const {
@@ -111,14 +132,17 @@ template <> struct MachineTraits<TargetX8632> {
void SetModRM(int mod, GPRRegister rm) {
assert((mod & ~3) == 0);
- encoding_[0] = (mod << 6) | rm;
+ encoding_[0] = (mod << 6) | (rm & 0x07);
+ rex_ = (rm & 0x08) ? RexB : RexNone;
length_ = 1;
}
void SetSIB(ScaleFactor scale, GPRRegister index, GPRRegister base) {
assert(length_ == 1);
assert((scale & ~3) == 0);
- encoding_[1] = (scale << 6) | (index << 3) | base;
+ encoding_[1] = (scale << 6) | ((index & 0x07) << 3) | (base & 0x07);
+ rex_ =
+ ((base & 0x08) ? RexB : RexNone) | ((index & 0x08) ? RexX : RexNone);
length_ = 2;
}
@@ -138,6 +162,7 @@ template <> struct MachineTraits<TargetX8632> {
private:
AssemblerFixup *fixup_;
+ uint8_t rex_ = 0;
uint8_t encoding_[6];
uint8_t length_;
@@ -155,7 +180,7 @@ template <> struct MachineTraits<TargetX8632> {
return ((encoding_[0] & 0xF8) ==
0xC0) // Addressing mode is register only.
&&
- ((encoding_[0] & 0x07) == reg); // Register codes match.
+ (rm() == reg); // Register codes match.
}
template <class> friend class AssemblerX86Base;
@@ -173,53 +198,54 @@ template <> struct MachineTraits<TargetX8632> {
}
Address(GPRRegister base, int32_t disp) {
- if (disp == 0 && base != RegX8632::Encoded_Reg_ebp) {
+ if (disp == 0 && (base & 7) != RegX8664::Encoded_Reg_ebp) {
SetModRM(0, base);
- if (base == RegX8632::Encoded_Reg_esp)
- SetSIB(TIMES_1, RegX8632::Encoded_Reg_esp, base);
+ if ((base & 7) == RegX8664::Encoded_Reg_esp)
+ SetSIB(TIMES_1, RegX8664::Encoded_Reg_esp, base);
} else if (Utils::IsInt(8, disp)) {
SetModRM(1, base);
- if (base == RegX8632::Encoded_Reg_esp)
- SetSIB(TIMES_1, RegX8632::Encoded_Reg_esp, base);
+ if ((base & 7) == RegX8664::Encoded_Reg_esp)
+ SetSIB(TIMES_1, RegX8664::Encoded_Reg_esp, base);
SetDisp8(disp);
} else {
SetModRM(2, base);
- if (base == RegX8632::Encoded_Reg_esp)
- SetSIB(TIMES_1, RegX8632::Encoded_Reg_esp, base);
+ if ((base & 7) == RegX8664::Encoded_Reg_esp)
+ SetSIB(TIMES_1, RegX8664::Encoded_Reg_esp, base);
SetDisp32(disp);
}
}
Address(GPRRegister index, ScaleFactor scale, int32_t disp) {
- assert(index != RegX8632::Encoded_Reg_esp); // Illegal addressing mode.
- SetModRM(0, RegX8632::Encoded_Reg_esp);
- SetSIB(scale, index, RegX8632::Encoded_Reg_ebp);
+ assert(index != RegX8664::Encoded_Reg_esp); // Illegal addressing mode.
+ SetModRM(0, RegX8664::Encoded_Reg_esp);
+ SetSIB(scale, index, RegX8664::Encoded_Reg_ebp);
SetDisp32(disp);
}
Address(GPRRegister base, GPRRegister index, ScaleFactor scale,
int32_t disp) {
- assert(index != RegX8632::Encoded_Reg_esp); // Illegal addressing mode.
- if (disp == 0 && base != RegX8632::Encoded_Reg_ebp) {
- SetModRM(0, RegX8632::Encoded_Reg_esp);
+ assert(index != RegX8664::Encoded_Reg_esp); // Illegal addressing mode.
+ if (disp == 0 && (base & 7) != RegX8664::Encoded_Reg_ebp) {
+ SetModRM(0, RegX8664::Encoded_Reg_esp);
SetSIB(scale, index, base);
} else if (Utils::IsInt(8, disp)) {
- SetModRM(1, RegX8632::Encoded_Reg_esp);
+ SetModRM(1, RegX8664::Encoded_Reg_esp);
SetSIB(scale, index, base);
SetDisp8(disp);
} else {
- SetModRM(2, RegX8632::Encoded_Reg_esp);
+ SetModRM(2, RegX8664::Encoded_Reg_esp);
SetSIB(scale, index, base);
SetDisp32(disp);
}
}
- /// AbsoluteTag is a special tag used by clients to create an absolute
- /// Address.
+ // PcRelTag is a special tag for requesting rip-relative addressing in
+ // X86-64.
+ // TODO(jpp): this is bogus. remove.
enum AbsoluteTag { ABSOLUTE };
Address(AbsoluteTag, const uintptr_t Addr) {
- SetModRM(0, RegX8632::Encoded_Reg_ebp);
+ SetModRM(0, RegX8664::Encoded_Reg_ebp);
SetDisp32(Addr);
}
@@ -229,7 +255,7 @@ template <> struct MachineTraits<TargetX8632> {
}
Address(AbsoluteTag, RelocOffsetT Offset, AssemblerFixup *Fixup) {
- SetModRM(0, RegX8632::Encoded_Reg_ebp);
+ SetModRM(0, RegX8664::Encoded_Reg_ebp);
// Use the Offset in the displacement for now. If we decide to process
// fixups later, we'll need to patch up the emitted displacement.
SetDisp32(Offset);
@@ -242,12 +268,15 @@ template <> struct MachineTraits<TargetX8632> {
}
static Address ofConstPool(Assembler *Asm, const Constant *Imm) {
+ // TODO(jpp): ???
AssemblerFixup *Fixup = Asm->createFixup(llvm::ELF::R_386_32, Imm);
const RelocOffsetT Offset = 0;
return Address(ABSOLUTE, Offset, Fixup);
}
};
+#if 0
Jim Stichnoth 2015/07/26 15:31:11 Why keep the "#if 0" commented-out code around?
John 2015/07/27 20:35:58 Because it would make my life a little bit easier
+ // The Traits for lowering/insts for x86-64 are very similar to the ones for x86-32, so these are kept here.
Jim Stichnoth 2015/07/26 15:31:11 80-col
John 2015/07/27 20:35:58 Done.
//----------------------------------------------------------------------------
// __ ______ __ __ ______ ______ __ __ __ ______
// /\ \ /\ __ \/\ \ _ \ \/\ ___\/\ == \/\ \/\ "-.\ \/\ ___\
@@ -272,7 +301,7 @@ template <> struct MachineTraits<TargetX8632> {
#define X(val, encode, name, name16, name8, scratch, preserved, stackptr, \
frameptr, isI8, isInt, isFP) \
name8,
- REGX8632_TABLE
+ REGX8664_TABLE
#undef X
};
@@ -280,7 +309,7 @@ template <> struct MachineTraits<TargetX8632> {
#define X(val, encode, name, name16, name8, scratch, preserved, stackptr, \
frameptr, isI8, isInt, isFP) \
name16,
- REGX8632_TABLE
+ REGX8664_TABLE
#undef X
};
@@ -288,7 +317,7 @@ template <> struct MachineTraits<TargetX8632> {
#define X(val, encode, name, name16, name8, scratch, preserved, stackptr, \
frameptr, isI8, isInt, isFP) \
name,
- REGX8632_TABLE
+ REGX8664_TABLE
#undef X
};
@@ -315,7 +344,7 @@ template <> struct MachineTraits<TargetX8632> {
(*FloatRegisters)[RegisterSet::val] = isFP; \
(*VectorRegisters)[RegisterSet::val] = isFP; \
(*ScratchRegs)[RegisterSet::val] = scratch;
- REGX8632_TABLE;
+ REGX8664_TABLE;
#undef X
}
@@ -343,7 +372,7 @@ template <> struct MachineTraits<TargetX8632> {
if (frameptr && (Exclude & ::Ice::TargetLowering::RegSet_FramePointer)) \
Registers[RegisterSet::val] = false;
- REGX8632_TABLE
+ REGX8664_TABLE
#undef X
@@ -358,7 +387,7 @@ template <> struct MachineTraits<TargetX8632> {
// information. Fix this in conjunction with the caller-side TODO.
assert(Permutation.size() >= RegisterSet::Reg_NUM);
// Expected upper bound on the number of registers in a single equivalence
- // class. For x86-32, this would comprise the 8 XMM registers. This is for
+ // class. For x86-64, this would comprise the 8 XMM registers. This is for
// performance, not correctness.
static const unsigned MaxEquivalenceClassSize = 8;
typedef llvm::SmallVector<int32_t, MaxEquivalenceClassSize> RegisterList;
@@ -381,7 +410,7 @@ template <> struct MachineTraits<TargetX8632> {
/* val is assigned to an equivalence class based on its properties. */ \
EquivalenceClasses[Index].push_back(RegisterSet::val); \
}
- REGX8632_TABLE
+ REGX8664_TABLE
#undef X
RandomNumberGeneratorWrapper RNG(Ctx->getRNG());
@@ -422,7 +451,7 @@ template <> struct MachineTraits<TargetX8632> {
static const uint32_t X86_MAX_XMM_ARGS = 4;
/// The number of bits in a byte
static const uint32_t X86_CHAR_BIT = 8;
- /// Stack alignment. This is defined in IceTargetLoweringX8632.cpp because it
+ /// Stack alignment. This is defined in IceTargetLoweringX8664.cpp because it
/// is used as an argument to std::max(), and the default std::less<T> has an
/// operator(T const&, T const&) which requires this member to have an
/// address.
@@ -444,12 +473,12 @@ template <> struct MachineTraits<TargetX8632> {
assert(isVectorType(Ty));
size_t Index = static_cast<size_t>(Ty);
(void)Index;
- assert(Index < TableTypeX8632AttributesSize);
- return TableTypeX8632Attributes[Ty].InVectorElementType;
+ assert(Index < TableTypeX8664AttributesSize);
+ return TableTypeX8664Attributes[Ty].InVectorElementType;
}
// Note: The following data structures are defined in
- // IceTargetLoweringX8632.cpp.
+ // IceTargetLoweringX8664.cpp.
/// The following table summarizes the logic for lowering the fcmp
/// instruction. There is one table entry for each of the 16 conditions.
@@ -504,10 +533,10 @@ template <> struct MachineTraits<TargetX8632> {
return TableIcmp32[Index].Mapping;
}
- static const struct TableTypeX8632AttributesType {
+ static const struct TableTypeX8664AttributesType {
Type InVectorElementType;
- } TableTypeX8632Attributes[];
- static const size_t TableTypeX8632AttributesSize;
+ } TableTypeX8664Attributes[];
+ static const size_t TableTypeX8664AttributesSize;
//----------------------------------------------------------------------------
// __ __ __ ______ ______
@@ -517,11 +546,14 @@ template <> struct MachineTraits<TargetX8632> {
// \/_/\/_/ \/_/\/_____/ \/_/
//
//----------------------------------------------------------------------------
- using Insts = ::Ice::X86Internal::Insts<TargetX8632>;
+ using Insts = ::Ice::X86Internal::Insts<TargetX8664>;
+
+ using TargetLowering = TargetX8664;
+#endif // 0
- using TargetLowering = ::Ice::X86Internal::TargetX86Base<TargetX8632>;
- using Assembler = X8632::AssemblerX8632;
+ using Assembler = X8664::AssemblerX8664;
+#if 0
/// X86Operand extends the Operand hierarchy. Its subclasses are
/// X86OperandMem and VariableSplit.
class X86Operand : public ::Ice::Operand {
@@ -530,13 +562,13 @@ template <> struct MachineTraits<TargetX8632> {
X86Operand &operator=(const X86Operand &) = delete;
public:
- enum OperandKindX8632 { k__Start = ::Ice::Operand::kTarget, kMem, kSplit };
+ enum OperandKindX8664 { k__Start = ::Ice::Operand::kTarget, kMem, kSplit };
using ::Ice::Operand::dump;
void dump(const Cfg *, Ostream &Str) const override;
protected:
- X86Operand(OperandKindX8632 Kind, Type Ty)
+ X86Operand(OperandKindX8664 Kind, Type Ty)
: Operand(static_cast<::Ice::Operand::OperandKind>(Kind), Ty) {}
};
@@ -552,7 +584,7 @@ template <> struct MachineTraits<TargetX8632> {
enum SegmentRegisters {
DefaultSegment = -1,
#define X(val, name, prefix) val,
- SEG_REGX8632_TABLE
+ SEG_REGX8664_TABLE
#undef X
SegReg_NUM
};
@@ -669,7 +701,7 @@ template <> struct MachineTraits<TargetX8632> {
Variable *LinkedTo;
};
- // Note: The following data structures are defined in IceInstX8632.cpp.
+ // Note: The following data structures are defined in IceInstX8664.cpp.
static const struct InstBrAttributesType {
Cond::BrCond Opposite;
@@ -692,14 +724,15 @@ template <> struct MachineTraits<TargetX8632> {
static const char *InstSegmentRegNames[];
static uint8_t InstSegmentPrefixes[];
+#endif // 0
};
} // end of namespace X86Internal
-namespace X8632 {
-using Traits = ::Ice::X86Internal::MachineTraits<TargetX8632>;
-} // end of namespace X8632
+namespace X8664 {
+using Traits = ::Ice::X86Internal::MachineTraits<TargetX8664>;
+} // end of namespace X8664
} // end of namespace Ice
-#endif // SUBZERO_SRC_ICETARGETLOWERINGX8632TRAITS_H
+#endif // SUBZERO_SRC_ICETARGETLOWERINGX8664TRAITS_H
« src/IceTargetLoweringX8664.def ('K') | « src/IceTargetLoweringX8664.def ('k') | unittest/IceAssemblerX8632Test.cpp » ('j') | unittest/IceAssemblerX8664Test.cpp » ('J')

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