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Unified Diff: src/IceTargetLoweringX8664Traits.h

Issue 1224173006: Adds the x86-64 assembler. (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master
Patch Set: Introduces the X8664 assembler and tests. No REX support yet. Created 5 years, 5 months ago
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« src/IceInstX8664.def ('K') | « src/IceTargetLoweringX8664.def ('k') | unittest/IceAssemblerX8632Test.cpp » ('j') | unittest/IceAssemblerX8632Test.cpp » ('J')
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Index: src/IceTargetLoweringX8664Traits.h
diff --git a/src/IceTargetLoweringX8632Traits.h b/src/IceTargetLoweringX8664Traits.h
similarity index 88%
copy from src/IceTargetLoweringX8632Traits.h
copy to src/IceTargetLoweringX8664Traits.h
index ca15ea525daf55d5153a02c5843c803128fb2194..de0e5b6aff9a4c4ba47603086bf77ecd2ca3dea6 100644
--- a/src/IceTargetLoweringX8632Traits.h
+++ b/src/IceTargetLoweringX8664Traits.h
@@ -1,4 +1,4 @@
-//===- subzero/src/IceTargetLoweringX8632Traits.h - x86-32 traits -*- C++ -*-=//
+//===- subzero/src/IceTargetLoweringX8664Traits.h - x86-64 traits -*- C++ -*-=//
//
// The Subzero Code Generator
//
@@ -8,38 +8,37 @@
//===----------------------------------------------------------------------===//
///
/// \file
-/// This file declares the X8632 Target Lowering Traits.
+/// This file declares the X8664 Target Lowering Traits.
///
//===----------------------------------------------------------------------===//
-#ifndef SUBZERO_SRC_ICETARGETLOWERINGX8632TRAITS_H
-#define SUBZERO_SRC_ICETARGETLOWERINGX8632TRAITS_H
+#ifndef SUBZERO_SRC_ICETARGETLOWERINGX8664TRAITS_H
+#define SUBZERO_SRC_ICETARGETLOWERINGX8664TRAITS_H
#include "IceAssembler.h"
-#include "IceConditionCodesX8632.h"
+#include "IceConditionCodesX8664.h"
#include "IceDefs.h"
#include "IceInst.h"
-#include "IceInstX8632.def"
+#include "IceInstX8664.def"
#include "IceOperand.h"
-#include "IceRegistersX8632.h"
-#include "IceTargetLoweringX8632.def"
+#include "IceRegistersX8664.h"
+#include "IceTargetLoweringX8664.def"
#include "IceTargetLowering.h"
namespace Ice {
-class TargetX8632;
+class TargetX8664;
-namespace X8632 {
-class AssemblerX8632;
-} // end of namespace X8632
+namespace X8664 {
+class AssemblerX8664;
+} // end of namespace X8664
namespace X86Internal {
template <class Machine> struct Insts;
template <class Machine> struct MachineTraits;
-template <class Machine> class TargetX86Base;
-template <> struct MachineTraits<TargetX8632> {
+template <> struct MachineTraits<TargetX8664> {
//----------------------------------------------------------------------------
// ______ ______ __ __
// /\ __ \/\ ___\/\ "-./ \
@@ -48,19 +47,23 @@ template <> struct MachineTraits<TargetX8632> {
// \/_/\/_/\/_____/\/_/ \/_/
//
//----------------------------------------------------------------------------
+ static constexpr bool Is64Bit = true;
+ static constexpr bool HasPopa = false;
+ static constexpr bool HasPusha = false;
+ static constexpr bool UsesX87 = false;
+
enum ScaleFactor { TIMES_1 = 0, TIMES_2 = 1, TIMES_4 = 2, TIMES_8 = 3 };
- using GPRRegister = ::Ice::RegX8632::GPRRegister;
- using XmmRegister = ::Ice::RegX8632::XmmRegister;
- using ByteRegister = ::Ice::RegX8632::ByteRegister;
- using X87STRegister = ::Ice::RegX8632::X87STRegister;
+ using GPRRegister = ::Ice::RegX8664::GPRRegister;
+ using XmmRegister = ::Ice::RegX8664::XmmRegister;
+ using ByteRegister = ::Ice::RegX8664::ByteRegister;
- using Cond = ::Ice::CondX86;
+ using Cond = ::Ice::CondX8664;
- using RegisterSet = ::Ice::RegX8632;
- static const GPRRegister Encoded_Reg_Accumulator = RegX8632::Encoded_Reg_eax;
- static const GPRRegister Encoded_Reg_Counter = RegX8632::Encoded_Reg_ecx;
- static const FixupKind PcRelFixup = llvm::ELF::R_386_PC32;
+ using RegisterSet = ::Ice::RegX8664;
+ static const GPRRegister Encoded_Reg_Accumulator = RegX8664::Encoded_Reg_eax;
+ static const GPRRegister Encoded_Reg_Counter = RegX8664::Encoded_Reg_ecx;
+ static const FixupKind PcRelFixup = llvm::ELF::R_386_PC32; // TODO(jpp): ???
jvoung (off chromium) 2015/07/23 17:59:36 FYI the llvm::ELF:: stuff comes from toolchain_bu
John 2015/07/27 20:35:58 Thanks for the pointer.
class Operand {
public:
@@ -173,42 +176,42 @@ template <> struct MachineTraits<TargetX8632> {
}
Address(GPRRegister base, int32_t disp) {
- if (disp == 0 && base != RegX8632::Encoded_Reg_ebp) {
+ if (disp == 0 && base != RegX8664::Encoded_Reg_ebp) {
SetModRM(0, base);
- if (base == RegX8632::Encoded_Reg_esp)
- SetSIB(TIMES_1, RegX8632::Encoded_Reg_esp, base);
+ if (base == RegX8664::Encoded_Reg_esp)
+ SetSIB(TIMES_1, RegX8664::Encoded_Reg_esp, base);
} else if (Utils::IsInt(8, disp)) {
SetModRM(1, base);
- if (base == RegX8632::Encoded_Reg_esp)
- SetSIB(TIMES_1, RegX8632::Encoded_Reg_esp, base);
+ if (base == RegX8664::Encoded_Reg_esp)
+ SetSIB(TIMES_1, RegX8664::Encoded_Reg_esp, base);
SetDisp8(disp);
} else {
SetModRM(2, base);
- if (base == RegX8632::Encoded_Reg_esp)
- SetSIB(TIMES_1, RegX8632::Encoded_Reg_esp, base);
+ if (base == RegX8664::Encoded_Reg_esp)
+ SetSIB(TIMES_1, RegX8664::Encoded_Reg_esp, base);
SetDisp32(disp);
}
}
Address(GPRRegister index, ScaleFactor scale, int32_t disp) {
- assert(index != RegX8632::Encoded_Reg_esp); // Illegal addressing mode.
- SetModRM(0, RegX8632::Encoded_Reg_esp);
- SetSIB(scale, index, RegX8632::Encoded_Reg_ebp);
+ assert(index != RegX8664::Encoded_Reg_esp); // Illegal addressing mode.
+ SetModRM(0, RegX8664::Encoded_Reg_esp);
+ SetSIB(scale, index, RegX8664::Encoded_Reg_ebp);
SetDisp32(disp);
}
Address(GPRRegister base, GPRRegister index, ScaleFactor scale,
int32_t disp) {
- assert(index != RegX8632::Encoded_Reg_esp); // Illegal addressing mode.
- if (disp == 0 && base != RegX8632::Encoded_Reg_ebp) {
- SetModRM(0, RegX8632::Encoded_Reg_esp);
+ assert(index != RegX8664::Encoded_Reg_esp); // Illegal addressing mode.
+ if (disp == 0 && base != RegX8664::Encoded_Reg_ebp) {
+ SetModRM(0, RegX8664::Encoded_Reg_esp);
SetSIB(scale, index, base);
} else if (Utils::IsInt(8, disp)) {
- SetModRM(1, RegX8632::Encoded_Reg_esp);
+ SetModRM(1, RegX8664::Encoded_Reg_esp);
SetSIB(scale, index, base);
SetDisp8(disp);
} else {
- SetModRM(2, RegX8632::Encoded_Reg_esp);
+ SetModRM(2, RegX8664::Encoded_Reg_esp);
SetSIB(scale, index, base);
SetDisp32(disp);
}
@@ -219,7 +222,7 @@ template <> struct MachineTraits<TargetX8632> {
enum AbsoluteTag { ABSOLUTE };
Address(AbsoluteTag, const uintptr_t Addr) {
- SetModRM(0, RegX8632::Encoded_Reg_ebp);
+ SetModRM(0, RegX8664::Encoded_Reg_ebp);
SetDisp32(Addr);
}
@@ -229,7 +232,7 @@ template <> struct MachineTraits<TargetX8632> {
}
Address(AbsoluteTag, RelocOffsetT Offset, AssemblerFixup *Fixup) {
- SetModRM(0, RegX8632::Encoded_Reg_ebp);
+ SetModRM(0, RegX8664::Encoded_Reg_ebp);
// Use the Offset in the displacement for now. If we decide to process
// fixups later, we'll need to patch up the emitted displacement.
SetDisp32(Offset);
@@ -242,12 +245,15 @@ template <> struct MachineTraits<TargetX8632> {
}
static Address ofConstPool(Assembler *Asm, const Constant *Imm) {
+ // TODO(jpp): ???
AssemblerFixup *Fixup = Asm->createFixup(llvm::ELF::R_386_32, Imm);
const RelocOffsetT Offset = 0;
return Address(ABSOLUTE, Offset, Fixup);
}
};
+#if 0
+ // The Traits for lowering/insts for x86-64 are very similar to the ones for x86-32, so these are kept here.
jvoung (off chromium) 2015/07/23 17:59:36 Just checking, but is the #if 0 necessary?
John 2015/07/27 20:35:58 It would help me out to keep implementing the back
//----------------------------------------------------------------------------
// __ ______ __ __ ______ ______ __ __ __ ______
// /\ \ /\ __ \/\ \ _ \ \/\ ___\/\ == \/\ \/\ "-.\ \/\ ___\
@@ -272,7 +278,7 @@ template <> struct MachineTraits<TargetX8632> {
#define X(val, encode, name, name16, name8, scratch, preserved, stackptr, \
frameptr, isI8, isInt, isFP) \
name8,
- REGX8632_TABLE
+ REGX8664_TABLE
#undef X
};
@@ -280,7 +286,7 @@ template <> struct MachineTraits<TargetX8632> {
#define X(val, encode, name, name16, name8, scratch, preserved, stackptr, \
frameptr, isI8, isInt, isFP) \
name16,
- REGX8632_TABLE
+ REGX8664_TABLE
#undef X
};
@@ -288,7 +294,7 @@ template <> struct MachineTraits<TargetX8632> {
#define X(val, encode, name, name16, name8, scratch, preserved, stackptr, \
frameptr, isI8, isInt, isFP) \
name,
- REGX8632_TABLE
+ REGX8664_TABLE
#undef X
};
@@ -315,7 +321,7 @@ template <> struct MachineTraits<TargetX8632> {
(*FloatRegisters)[RegisterSet::val] = isFP; \
(*VectorRegisters)[RegisterSet::val] = isFP; \
(*ScratchRegs)[RegisterSet::val] = scratch;
- REGX8632_TABLE;
+ REGX8664_TABLE;
#undef X
}
@@ -343,7 +349,7 @@ template <> struct MachineTraits<TargetX8632> {
if (frameptr && (Exclude & ::Ice::TargetLowering::RegSet_FramePointer)) \
Registers[RegisterSet::val] = false;
- REGX8632_TABLE
+ REGX8664_TABLE
#undef X
@@ -358,7 +364,7 @@ template <> struct MachineTraits<TargetX8632> {
// information. Fix this in conjunction with the caller-side TODO.
assert(Permutation.size() >= RegisterSet::Reg_NUM);
// Expected upper bound on the number of registers in a single equivalence
- // class. For x86-32, this would comprise the 8 XMM registers. This is for
+ // class. For x86-64, this would comprise the 8 XMM registers. This is for
// performance, not correctness.
static const unsigned MaxEquivalenceClassSize = 8;
typedef llvm::SmallVector<int32_t, MaxEquivalenceClassSize> RegisterList;
@@ -381,7 +387,7 @@ template <> struct MachineTraits<TargetX8632> {
/* val is assigned to an equivalence class based on its properties. */ \
EquivalenceClasses[Index].push_back(RegisterSet::val); \
}
- REGX8632_TABLE
+ REGX8664_TABLE
#undef X
RandomNumberGeneratorWrapper RNG(Ctx->getRNG());
@@ -422,7 +428,7 @@ template <> struct MachineTraits<TargetX8632> {
static const uint32_t X86_MAX_XMM_ARGS = 4;
/// The number of bits in a byte
static const uint32_t X86_CHAR_BIT = 8;
- /// Stack alignment. This is defined in IceTargetLoweringX8632.cpp because it
+ /// Stack alignment. This is defined in IceTargetLoweringX8664.cpp because it
/// is used as an argument to std::max(), and the default std::less<T> has an
/// operator(T const&, T const&) which requires this member to have an
/// address.
@@ -444,12 +450,12 @@ template <> struct MachineTraits<TargetX8632> {
assert(isVectorType(Ty));
size_t Index = static_cast<size_t>(Ty);
(void)Index;
- assert(Index < TableTypeX8632AttributesSize);
- return TableTypeX8632Attributes[Ty].InVectorElementType;
+ assert(Index < TableTypeX8664AttributesSize);
+ return TableTypeX8664Attributes[Ty].InVectorElementType;
}
// Note: The following data structures are defined in
- // IceTargetLoweringX8632.cpp.
+ // IceTargetLoweringX8664.cpp.
/// The following table summarizes the logic for lowering the fcmp
/// instruction. There is one table entry for each of the 16 conditions.
@@ -504,10 +510,10 @@ template <> struct MachineTraits<TargetX8632> {
return TableIcmp32[Index].Mapping;
}
- static const struct TableTypeX8632AttributesType {
+ static const struct TableTypeX8664AttributesType {
Type InVectorElementType;
- } TableTypeX8632Attributes[];
- static const size_t TableTypeX8632AttributesSize;
+ } TableTypeX8664Attributes[];
+ static const size_t TableTypeX8664AttributesSize;
//----------------------------------------------------------------------------
// __ __ __ ______ ______
@@ -517,10 +523,10 @@ template <> struct MachineTraits<TargetX8632> {
// \/_/\/_/ \/_/\/_____/ \/_/
//
//----------------------------------------------------------------------------
- using Insts = ::Ice::X86Internal::Insts<TargetX8632>;
+ using Insts = ::Ice::X86Internal::Insts<TargetX8664>;
- using TargetLowering = ::Ice::X86Internal::TargetX86Base<TargetX8632>;
- using Assembler = X8632::AssemblerX8632;
+ using TargetLowering = TargetX8664;
+ using Assembler = X8664::AssemblerX8664;
/// X86Operand extends the Operand hierarchy. Its subclasses are
/// X86OperandMem and VariableSplit.
@@ -530,13 +536,13 @@ template <> struct MachineTraits<TargetX8632> {
X86Operand &operator=(const X86Operand &) = delete;
public:
- enum OperandKindX8632 { k__Start = ::Ice::Operand::kTarget, kMem, kSplit };
+ enum OperandKindX8664 { k__Start = ::Ice::Operand::kTarget, kMem, kSplit };
using ::Ice::Operand::dump;
void dump(const Cfg *, Ostream &Str) const override;
protected:
- X86Operand(OperandKindX8632 Kind, Type Ty)
+ X86Operand(OperandKindX8664 Kind, Type Ty)
: Operand(static_cast<::Ice::Operand::OperandKind>(Kind), Ty) {}
};
@@ -552,7 +558,7 @@ template <> struct MachineTraits<TargetX8632> {
enum SegmentRegisters {
DefaultSegment = -1,
#define X(val, name, prefix) val,
- SEG_REGX8632_TABLE
+ SEG_REGX8664_TABLE
#undef X
SegReg_NUM
};
@@ -669,7 +675,7 @@ template <> struct MachineTraits<TargetX8632> {
Variable *LinkedTo;
};
- // Note: The following data structures are defined in IceInstX8632.cpp.
+ // Note: The following data structures are defined in IceInstX8664.cpp.
static const struct InstBrAttributesType {
Cond::BrCond Opposite;
@@ -692,14 +698,15 @@ template <> struct MachineTraits<TargetX8632> {
static const char *InstSegmentRegNames[];
static uint8_t InstSegmentPrefixes[];
+#endif // 0
};
} // end of namespace X86Internal
-namespace X8632 {
-using Traits = ::Ice::X86Internal::MachineTraits<TargetX8632>;
-} // end of namespace X8632
+namespace X8664 {
+using Traits = ::Ice::X86Internal::MachineTraits<TargetX8664>;
+} // end of namespace X8664
} // end of namespace Ice
-#endif // SUBZERO_SRC_ICETARGETLOWERINGX8632TRAITS_H
+#endif // SUBZERO_SRC_ICETARGETLOWERINGX8664TRAITS_H
« src/IceInstX8664.def ('K') | « src/IceTargetLoweringX8664.def ('k') | unittest/IceAssemblerX8632Test.cpp » ('j') | unittest/IceAssemblerX8632Test.cpp » ('J')

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