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Issue 1224173006: Adds the x86-64 assembler. (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master
Patch Set: Introduces the X8664 assembler and tests. No REX support yet. Created 5 years, 5 months ago
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« src/IceAssemblerX86Base.h ('K') | « src/IceConditionCodesX8664.h ('k') | src/IceTargetLoweringX8632Traits.h » ('j') | src/IceTargetLoweringX8664Traits.h » ('J')
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1 //===- subzero/src/IceInstX8664.def - X-macros for x86-64 insts -*- C++ -*-===// 1 //===- subzero/src/IceInstX8664.def - X-macros for x86-64 insts -*- C++ -*-===//
2 // 2 //
3 // The Subzero Code Generator 3 // The Subzero Code Generator
4 // 4 //
5 // This file is distributed under the University of Illinois Open Source 5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details. 6 // License. See LICENSE.TXT for details.
7 // 7 //
8 //===----------------------------------------------------------------------===// 8 //===----------------------------------------------------------------------===//
9 // 9 //
10 // This file defines properties of lowered x86-64 instructions in the 10 // This file defines properties of lowered x86-64 instructions in the
11 // form of x-macros. 11 // form of x-macros.
12 // 12 //
13 //===----------------------------------------------------------------------===// 13 //===----------------------------------------------------------------------===//
14 14
15 #ifndef SUBZERO_SRC_ICEINSTX8664_DEF 15 #ifndef SUBZERO_SRC_ICEINSTX8664_DEF
16 #define SUBZERO_SRC_ICEINSTX8664_DEF 16 #define SUBZERO_SRC_ICEINSTX8664_DEF
17 17
18 // NOTE: we use the 32bit register names for two reasons:
19 // (1) it makes it easier to implement the x86 assembler template.
20 // (2) when generating code, subzero defaults to using 32 bit registers, s o using the 32 bit register name would hopefully make this design more explicit.
jvoung (off chromium) 2015/07/23 17:59:36 Default of 32-bit is interesting... I suppose that
jvoung (off chromium) 2015/07/23 17:59:36 80 col?
John 2015/07/27 20:35:57 Done.
John 2015/07/27 20:35:57 Yup, if you need 64 operands than you need a rex p
John 2015/07/27 20:35:58 Done.
18 // NOTE: esp is not considered isInt, to avoid register allocating it. 21 // NOTE: esp is not considered isInt, to avoid register allocating it.
19 #define REGX8664_GPR_TABLE \ 22 #define REGX8664_GPR_TABLE \
20 /* val, encode, name64, name, name16, name8, scratch, preserved, stackptr, \ 23 /* val, encode, name64, name, name16, name8, scratch, preserved, stackptr, \
21 frameptr, isInt, isFP */ \ 24 frameptr, isInt, isFP */ \
22 X(Reg_rax, = 0, "rax", "eax" , "ax" , "al" , 1, 0, 0, 0, 1, 0) \ 25 X(Reg_eax, = 0, "rax", "eax" , "ax" , "al" , 1, 0, 0, 0, 1, 0) \
23 X(Reg_rcx, = Reg_rax + 1, "rcx", "ecx" , "cx" , "cl" , 1, 0, 0, 0, 1, 0) \ 26 X(Reg_ecx, = 1, "rcx", "ecx" , "cx" , "cl" , 1, 0, 0, 0, 1, 0) \
24 X(Reg_rdx, = Reg_rax + 2, "rdx", "edx" , "dx" , "dl" , 1, 0, 0, 0, 1, 0) \ 27 X(Reg_edx, = 2, "rdx", "edx" , "dx" , "dl" , 1, 0, 0, 0, 1, 0) \
25 X(Reg_rbx, = Reg_rax + 3, "rbx", "ebx" , "bx" , "bl" , 0, 1, 0, 0, 1, 0) \ 28 X(Reg_ebx, = 3, "rbx", "ebx" , "bx" , "bl" , 0, 1, 0, 0, 1, 0) \
26 X(Reg_rsp, = Reg_rax + 4, "rsp", "esp" , "sp" , "spl" , 0, 0, 1, 0, 0, 0) \ 29 X(Reg_esp, = 4, "rsp", "esp" , "sp" , "spl" , 0, 0, 1, 0, 0, 0) \
27 X(Reg_rbp, = Reg_rax + 5, "rbp", "ebp" , "bp" , "bpl" , 0, 0, 0, 1, 1, 0) \ 30 X(Reg_ebp, = 5, "rbp", "ebp" , "bp" , "bpl" , 0, 0, 0, 1, 1, 0) \
28 X(Reg_rsi, = Reg_rax + 6, "rsi", "esi" , "si" , "sil" , 1, 0, 0, 0, 1, 0) \ 31 X(Reg_esi, = 6, "rsi", "esi" , "si" , "sil" , 1, 0, 0, 0, 1, 0) \
29 X(Reg_rdi, = Reg_rax + 7, "rdi", "edi" , "di" , "dil" , 1, 0, 0, 0, 1, 0) \ 32 X(Reg_edi, = 7, "rdi", "edi" , "di" , "dil" , 1, 0, 0, 0, 1, 0) \
30 X(Reg_r8, = Reg_rax + 8, "r8" , "r8d" , "r8w", "r8l" , 1, 0, 0, 0, 1, 0) \ 33 X(Reg_r8w, = 8, "r8" , "r8d" , "r8w", "r8l" , 1, 0, 0, 0, 1, 0) \
31 X(Reg_r9, = Reg_rax + 9, "r9" , "r9d" , "r9w", "r9l" , 1, 0, 0, 0, 1, 0) \ 34 X(Reg_r9w, = 9, "r9" , "r9d" , "r9w", "r9l" , 1, 0, 0, 0, 1, 0) \
32 X(Reg_r10, = Reg_rax + 10, "r10", "r10d", "r10w", "r10l", 1, 0, 0, 0, 1, 0) \ 35 X(Reg_r10w, = 10, "r10", "r10d", "r10w", "r10l", 1, 0, 0, 0, 1, 0) \
33 X(Reg_r11, = Reg_rax + 11, "r11", "r11d", "r11w", "r11l", 1, 0, 0, 0, 1, 0) \ 36 X(Reg_r11w, = 11, "r11", "r11d", "r11w", "r11l", 1, 0, 0, 0, 1, 0) \
34 X(Reg_r12, = Reg_rax + 12, "r12", "r12d", "r12w", "r12l", 0, 1, 0, 0, 1, 0) \ 37 X(Reg_r12w, = 12, "r12", "r12d", "r12w", "r12l", 0, 1, 0, 0, 1, 0) \
35 X(Reg_r13, = Reg_rax + 13, "r13", "r13d", "r13w", "r12l", 0, 1, 0, 0, 1, 0) \ 38 X(Reg_r13w, = 13, "r13", "r13d", "r13w", "r12l", 0, 1, 0, 0, 1, 0) \
36 X(Reg_r14, = Reg_rax + 14, "r14", "r14d", "r14w", "r14l", 0, 1, 0, 0, 1, 0) \ 39 X(Reg_r14w, = 14, "r14", "r14d", "r14w", "r14l", 0, 1, 0, 0, 1, 0) \
37 X(Reg_r15, = Reg_rax + 15, "r15", "r15d", "r15w", "r15l", 0, 1, 0, 0, 1, 0) 40 X(Reg_r15w, = 15, "r15", "r15d", "r15w", "r15l", 0, 1, 0, 0, 1, 0)
38 41
39 #define REGX8664_XMM_TABLE \ 42 #define REGX8664_XMM_TABLE \
40 /* val, encode, name64, name, name16, name8, scratch, preserved, stackptr, \ 43 /* val, encode, name64, name, name16, name8, scratch, preserved, stackptr, \
41 frameptr, isInt, isFP */ \ 44 frameptr, isInt, isFP */ \
42 X(Reg_xmm0, = 0, "xmm0" , "", "", "", 1, 0, 0, 0, 0, 1) \ 45 X(Reg_xmm0, = 0, "xmm0" , "", "", "", 1, 0, 0, 0, 0, 1) \
43 X(Reg_xmm1, = Reg_xmm0 + 1, "xmm1" , "", "", "", 1, 0, 0, 0, 0, 1) \ 46 X(Reg_xmm1, = 1, "xmm1" , "", "", "", 1, 0, 0, 0, 0, 1) \
44 X(Reg_xmm2, = Reg_xmm0 + 2, "xmm2" , "", "", "", 1, 0, 0, 0, 0, 1) \ 47 X(Reg_xmm2, = 2, "xmm2" , "", "", "", 1, 0, 0, 0, 0, 1) \
45 X(Reg_xmm3, = Reg_xmm0 + 3, "xmm3" , "", "", "", 1, 0, 0, 0, 0, 1) \ 48 X(Reg_xmm3, = 3, "xmm3" , "", "", "", 1, 0, 0, 0, 0, 1) \
46 X(Reg_xmm4, = Reg_xmm0 + 4, "xmm4" , "", "", "", 1, 0, 0, 0, 0, 1) \ 49 X(Reg_xmm4, = 4, "xmm4" , "", "", "", 1, 0, 0, 0, 0, 1) \
47 X(Reg_xmm5, = Reg_xmm0 + 5, "xmm5" , "", "", "", 1, 0, 0, 0, 0, 1) \ 50 X(Reg_xmm5, = 5, "xmm5" , "", "", "", 1, 0, 0, 0, 0, 1) \
48 X(Reg_xmm6, = Reg_xmm0 + 6, "xmm6" , "", "", "", 1, 0, 0, 0, 0, 1) \ 51 X(Reg_xmm6, = 6, "xmm6" , "", "", "", 1, 0, 0, 0, 0, 1) \
49 X(Reg_xmm7, = Reg_xmm0 + 7, "xmm7" , "", "", "", 1, 0, 0, 0, 0, 1) \ 52 X(Reg_xmm7, = 7, "xmm7" , "", "", "", 1, 0, 0, 0, 0, 1) \
50 X(Reg_xmm8, = Reg_xmm0 + 8, "xmm8" , "", "", "", 1, 0, 0, 0, 0, 1) \ 53 X(Reg_xmm8, = 8, "xmm8" , "", "", "", 1, 0, 0, 0, 0, 1) \
51 X(Reg_xmm9, = Reg_xmm0 + 9, "xmm9" , "", "", "", 1, 0, 0, 0, 0, 1) \ 54 X(Reg_xmm9, = 9, "xmm9" , "", "", "", 1, 0, 0, 0, 0, 1) \
52 X(Reg_xmm10, = Reg_xmm0 + 10, "xmm10", "", "", "", 1, 0, 0, 0, 0, 1) \ 55 X(Reg_xmm10, = 10, "xmm10", "", "", "", 1, 0, 0, 0, 0, 1) \
53 X(Reg_xmm11, = Reg_xmm0 + 11, "xmm11", "", "", "", 1, 0, 0, 0, 0, 1) \ 56 X(Reg_xmm11, = 11, "xmm11", "", "", "", 1, 0, 0, 0, 0, 1) \
54 X(Reg_xmm12, = Reg_xmm0 + 12, "xmm12", "", "", "", 1, 0, 0, 0, 0, 1) \ 57 X(Reg_xmm12, = 12, "xmm12", "", "", "", 1, 0, 0, 0, 0, 1) \
55 X(Reg_xmm13, = Reg_xmm0 + 13, "xmm13", "", "", "", 1, 0, 0, 0, 0, 1) \ 58 X(Reg_xmm13, = 13, "xmm13", "", "", "", 1, 0, 0, 0, 0, 1) \
56 X(Reg_xmm14, = Reg_xmm0 + 14, "xmm14", "", "", "", 1, 0, 0, 0, 0, 1) \ 59 X(Reg_xmm14, = 14, "xmm14", "", "", "", 1, 0, 0, 0, 0, 1) \
57 X(Reg_xmm15, = Reg_xmm0 + 15, "xmm15", "", "", "", 1, 0, 0, 0, 0, 1) 60 X(Reg_xmm15, = 15, "xmm15", "", "", "", 1, 0, 0, 0, 0, 1)
58 //#define X(val, encode, name, name32, name16, name8, scratch, preserved, 61 //#define X(val, encode, name, name32, name16, name8, scratch, preserved,
59 // stackptr, frameptr, isI8, isInt, isFP) 62 // stackptr, frameptr, isI8, isInt, isFP)
60 63
61 // We also provide a combined table, so that there is a namespace where 64 // We also provide a combined table, so that there is a namespace where
62 // all of the registers are considered and have distinct numberings. 65 // all of the registers are considered and have distinct numberings.
63 // This is in contrast to the above, where the "encode" is based on how 66 // This is in contrast to the above, where the "encode" is based on how
64 // the register numbers will be encoded in binaries and values can overlap. 67 // the register numbers will be encoded in binaries and values can overlap.
65 // We don't want the register allocator choosing Reg_ah, in particular 68 // We don't want the register allocator choosing Reg_ah, in particular
66 // for lowering insertelement to pinsrb where internally we use an 69 // for lowering insertelement to pinsrb where internally we use an
67 // 8-bit operand but externally pinsrb uses a 32-bit register, in 70 // 8-bit operand but externally pinsrb uses a 32-bit register, in
68 // which Reg_ah doesn't map to eax. 71 // which Reg_ah doesn't map to eax.
69 #define REGX8664_TABLE \ 72 #define REGX8664_TABLE \
70 /* val, encode, name64, name, name16, name8, scratch, preserved, \ 73 /* val, encode, name64, name, name16, name8, scratch, preserved, \
71 stackptr, frameptr, isInt, isFP */ \ 74 stackptr, frameptr, isInt, isFP */ \
72 REGX8664_GPR_TABLE \ 75 REGX8664_GPR_TABLE \
73 X(Reg_ah, = Reg_rax + 4, "?ah", "?ah", "?ah", "ah", 0, 0, 0, 0, 0, 0) \ 76 X(Reg_ah, = Reg_rax + 4, "?ah", "?ah", "?ah", "ah", 0, 0, 0, 0, 0, 0) \
74 REGX8664_XMM_TABLE 77 REGX8664_XMM_TABLE
75 //#define X(val, encode, name, name32, name16, name8, scratch, preserved, 78 //#define X(val, encode, name, name32, name16, name8, scratch, preserved,
76 // stackptr, frameptr, isI8, isInt, isFP) 79 // stackptr, frameptr, isI8, isInt, isFP)
77 80
78 #define REGX8664_TABLE_BOUNDS \ 81 #define REGX8664_TABLE_BOUNDS \
79 /* val , init */ \ 82 /* val , init */ \
80 X(Reg_GPR_First, = Reg_rax ) \ 83 X(Reg_GPR_First, = Reg_eax ) \
81 X(Reg_GPR_Last , = Reg_r15 ) \ 84 X(Reg_GPR_Last , = Reg_r15w ) \
82 X(Reg_XMM_First, = Reg_xmm0 ) \ 85 X(Reg_XMM_First, = Reg_xmm0 ) \
83 X(Reg_XMM_Last , = Reg_xmm15) 86 X(Reg_XMM_Last , = Reg_xmm15)
84 // define X(val, init) 87 // define X(val, init)
85 88
86 // We also need the encodings for the Byte registers (other info overlaps 89 // We also need the encodings for the Byte registers (other info overlaps
87 // what is in the REGX8664_GPR_TABLE). We don't expose the ah, ch, dh, 90 // what is in the REGX8664_GPR_TABLE). We don't expose the ah, ch, dh,
88 // bh registers to keep register selection simple. 91 // bh registers to keep register selection simple.
89 #define REGX8664_BYTEREG_TABLE \ 92 #define REGX8664_BYTEREG_TABLE \
90 /* val , encode */ \ 93 /* val , encode */ \
91 X(Reg_al , = 0) \ 94 X(Reg_al , = 0) \
(...skipping 59 matching lines...) Expand 10 before | Expand all | Expand 10 after
151 X(IceType_v4i1 , IceType_i32 , "?" , "" , "d" , "" , "" ) \ 154 X(IceType_v4i1 , IceType_i32 , "?" , "" , "d" , "" , "" ) \
152 X(IceType_v8i1 , IceType_i16 , "?" , "" , "w" , "" , "" ) \ 155 X(IceType_v8i1 , IceType_i16 , "?" , "" , "w" , "" , "" ) \
153 X(IceType_v16i1, IceType_i8 , "?" , "" , "b" , "" , "" ) \ 156 X(IceType_v16i1, IceType_i8 , "?" , "" , "b" , "" , "" ) \
154 X(IceType_v16i8, IceType_i8 , "?" , "" , "b" , "" , "" ) \ 157 X(IceType_v16i8, IceType_i8 , "?" , "" , "b" , "" , "" ) \
155 X(IceType_v8i16, IceType_i16 , "?" , "" , "w" , "" , "" ) \ 158 X(IceType_v8i16, IceType_i16 , "?" , "" , "w" , "" , "" ) \
156 X(IceType_v4i32, IceType_i32 , "dq", "" , "d" , "" , "" ) \ 159 X(IceType_v4i32, IceType_i32 , "dq", "" , "d" , "" , "" ) \
157 X(IceType_v4f32, IceType_f32 , "ps", "" , "d" , "" , "" ) 160 X(IceType_v4f32, IceType_f32 , "ps", "" , "d" , "" , "" )
158 //#define X(tag, elementty, cvt, sdss, pack, width, fld) 161 //#define X(tag, elementty, cvt, sdss, pack, width, fld)
159 162
160 #endif // SUBZERO_SRC_ICEINSTX8664_DEF 163 #endif // SUBZERO_SRC_ICEINSTX8664_DEF
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« src/IceAssemblerX86Base.h ('K') | « src/IceConditionCodesX8664.h ('k') | src/IceTargetLoweringX8632Traits.h » ('j') | src/IceTargetLoweringX8664Traits.h » ('J')

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