Factor out prelowerPhi for 32-bit targets. Disable adv phi lowering for ARM.

src/IceClFlags.cpp

Index: src/IceClFlags.cpp
diff --git a/src/IceClFlags.cpp b/src/IceClFlags.cpp
index f1aebd2dfc42a9fb1724a543f122a702377027ec..2d2e641eb50133ee090eae36264e01a38a382c2f 100644
--- a/src/IceClFlags.cpp
+++ b/src/IceClFlags.cpp
@@ -390,7 +390,15 @@ void ClFlags::getParsedClFlags(ClFlags &OutFlags) {
   OutFlags.setFunctionSections(::FunctionSections);
   OutFlags.setNumTranslationThreads(::NumThreads);
   OutFlags.setOptLevel(::OLevel);
-  OutFlags.setPhiEdgeSplit(::EnablePhiEdgeSplit);
+  if (::TargetArch == Target_ARM32) {
+    // TODO(jvoung): We need lowerPhiAssignments to handle spilling
+    // more than one register, since some ARM lowerAssign sequences
+    // may require more than one register. For now, disable PhiEdgeSplit
+    // to avoid requiring lowerPhiAssignments.
+    OutFlags.setPhiEdgeSplit(false);
+  } else {
+    OutFlags.setPhiEdgeSplit(::EnablePhiEdgeSplit);
+  }
   OutFlags.setRandomSeed(::RandomSeed);
   OutFlags.setShouldDoNopInsertion(::ShouldDoNopInsertion);
   OutFlags.setShouldRandomizeRegAlloc(::RandomizeRegisterAllocation);