Factor out prelowerPhi for 32-bit targets. Disable adv phi lowering for ARM.

tests_lit/llvm2ice_tests/64bit.pnacl.ll

 ; This tries to be a comprehensive test of i64 operations, in
 ; particular the patterns for lowering i64 operations into constituent
 ; i32 operations on x86-32.
 
 ; RUN: %if --need=target_X8632 --command %p2i --filetype=obj --disassemble \
 ; RUN:   --target x8632 -i %s --args -O2 \
 ; RUN:   | %if --need=target_X8632 --command FileCheck %s
 
 ; RUN: %if --need=target_X8632 --command %p2i --filetype=obj --disassemble \
 ; RUN:   --target x8632 -i %s --args -Om1 \
@@ skipping 140 matching lines @@
 ; ARM32:      movw    [[REG2:r.*]], {{.*}} ; 0x5678
 ; ARM32:      movt    [[REG2:r.*]], {{.*}} ; 0x1234
 ; ARM32:      str     [[REG1]], [sp, #4]
 ; ARM32:      str     [[REG2]], [sp]
 ; ARM32:      {{mov|ldr}} r0
 ; ARM32:      {{mov|ldr}} r1
 ; ARM32:      movw    r2, #123
 ; ARM32:      bl      {{.*}} ignore64BitArgNoInline
 ; ARM32:      add     sp, {{.*}} #16
 
+define internal i32 @pass64BitUndefArg() {
+entry:
+  %call = call i32 @ignore64BitArgNoInline(i64 0, i32 123, i64 undef)
+  ret i32 %call
+}
+; CHECK-LABEL: pass64BitUndefArg
+; CHECK: sub esp
+; CHECK: mov DWORD PTR{{.*}},0x7b
+; CHECK: mov DWORD PTR{{.*}},0x0
+; CHECK: call {{.*}} R_{{.*}} ignore64BitArgNoInline
+; OPTM1-LABEL: pass64BitUndefArg
+; OPTM1: sub esp
+; OPTM1: mov DWORD PTR{{.*}},0x7b
+; OPTM1: mov DWORD PTR{{.*}},0x0
+; OPTM1: call {{.*}} R_{{.*}} ignore64BitArgNoInline
+; ARM32-LABEL: pass64BitUndefArg
+; ARM32: sub sp
+; ARM32: movw {{.*}}, #0
+; ARM32: str
+; ARM32: movw {{.*}}, #123
+; ARM32: bl {{.*}} ignore64BitArgNoInline
+
 define internal i64 @return64BitArg(i64 %padding, i64 %a) {
 entry:
   ret i64 %a
 }
 ; CHECK-LABEL: return64BitArg
 ; CHECK: mov     {{.*}},DWORD PTR [esp+0xc]
 ; CHECK: mov     {{.*}},DWORD PTR [esp+0x10]
 ;
 ; OPTM1-LABEL: return64BitArg
 ; OPTM1: mov     {{.*}},DWORD PTR [esp+0xc]
@@ skipping 1566 matching lines @@
   ret void
 }
 ; The following checks are not strictly necessary since one of the RUN
 ; lines actually runs the output through the assembler.
 ; CHECK-LABEL: icmpLt64Imm
 ; CHECK-NOT: cmp 0x{{[0-9a-f]+}},
 ; OPTM1-LABEL: icmpLt64Imm
 ; OPTM1-NOT: cmp 0x{{[0-9a-f]+}},
 ; ARM32-LABEL: icmpLt64Imm
 ; ARM32-NOT: cmp #{{[0-9a-f]+}},
+
+define internal i64 @phi64Imm(i32 %x, i64 %y, i64 %z) {
+entry:
+  %cond = icmp eq i32 %x, 88
+  br i1 %cond, label %branch1, label %branch2
+branch1:
+  %tmp = add i64 %y, %z
+  br label %branch2
+
+branch2:
+  %merge = phi i64 [ %tmp, %branch1 ], [ 20014547621496, %entry ]
+  ret i64 %merge
+}
+; CHECK-LABEL: phi64Imm
+; CHECK: mov {{.*}},0x5678
+; CHECK: mov {{.*}},0x1234
+; OPTM1-LABEL: phi64Imm
+; OPTM1: mov {{.*}},0x5678
+; OPTM1: mov {{.*}},0x1234
+; ARM32-LABEL: phi64Imm
+; ARM32: movw {{.*}}, #22136 ; 0x5678
+; ARM32: movw {{.*}}, #4660  ; 0x1234
+
+define internal i64 @phi64Undef(i32 %x, i64 %y, i64 %z) {
+entry:
+  %cond = icmp eq i32 %x, 88
+  br i1 %cond, label %branch1, label %branch2
+branch1:
+  %tmp = add i64 %y, %z
+  br label %branch2
+
+branch2:
+  %merge = phi i64 [ %tmp, %branch1 ], [ undef, %entry ]
+  ret i64 %merge
+}
+
+; CHECK-LABEL: phi64Undef
+; CHECK: mov {{.*}},0x0
+; CHECK: mov {{.*}},0x0
+; OPTM1-LABEL: phi64Undef
+; OPTM1: mov {{.*}},0x0
+; OPTM1: mov {{.*}},0x0
+; ARM32-LABEL: phi64Undef
+; ARM32: mov {{.*}} #0
+; ARM32: mov {{.*}} #0
+