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Side by Side Diff: src/IceTargetLoweringARM32.cpp

Issue 1223133007: Factor out prelowerPhi for 32-bit targets. Disable adv phi lowering for ARM. (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master
Patch Set: fill in wqthe random test case for more undef stuff Created 5 years, 5 months ago
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1 //===- subzero/src/IceTargetLoweringARM32.cpp - ARM32 lowering ------------===// 1 //===- subzero/src/IceTargetLoweringARM32.cpp - ARM32 lowering ------------===//
2 // 2 //
3 // The Subzero Code Generator 3 // The Subzero Code Generator
4 // 4 //
5 // This file is distributed under the University of Illinois Open Source 5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details. 6 // License. See LICENSE.TXT for details.
7 // 7 //
8 //===----------------------------------------------------------------------===// 8 //===----------------------------------------------------------------------===//
9 /// 9 ///
10 /// \file 10 /// \file
11 /// This file implements the TargetLoweringARM32 class, which consists almost 11 /// This file implements the TargetLoweringARM32 class, which consists almost
12 /// entirely of the lowering sequence for each high-level instruction. 12 /// entirely of the lowering sequence for each high-level instruction.
13 /// 13 ///
14 //===----------------------------------------------------------------------===// 14 //===----------------------------------------------------------------------===//
15 15
16 #include "IceTargetLoweringARM32.h" 16 #include "IceTargetLoweringARM32.h"
17 17
18 #include "IceCfg.h" 18 #include "IceCfg.h"
19 #include "IceCfgNode.h" 19 #include "IceCfgNode.h"
20 #include "IceClFlags.h" 20 #include "IceClFlags.h"
21 #include "IceDefs.h" 21 #include "IceDefs.h"
22 #include "IceELFObjectWriter.h" 22 #include "IceELFObjectWriter.h"
23 #include "IceGlobalInits.h" 23 #include "IceGlobalInits.h"
24 #include "IceInstARM32.h" 24 #include "IceInstARM32.h"
25 #include "IceLiveness.h" 25 #include "IceLiveness.h"
26 #include "IceOperand.h" 26 #include "IceOperand.h"
27 #include "IcePhiLoweringImpl.h"
27 #include "IceRegistersARM32.h" 28 #include "IceRegistersARM32.h"
28 #include "IceTargetLoweringARM32.def" 29 #include "IceTargetLoweringARM32.def"
29 #include "IceUtils.h" 30 #include "IceUtils.h"
30 #include "llvm/Support/MathExtras.h" 31 #include "llvm/Support/MathExtras.h"
31 32
32 namespace Ice { 33 namespace Ice {
33 34
34 namespace { 35 namespace {
35 36
36 void UnimplementedError(const ClFlags &Flags) { 37 void UnimplementedError(const ClFlags &Flags) {
(...skipping 2366 matching lines...) Expand 10 before | Expand all | Expand 10 after
2403 _cmp(Src0Var, Value); 2404 _cmp(Src0Var, Value);
2404 _br(Inst->getLabel(I), CondARM32::EQ); 2405 _br(Inst->getLabel(I), CondARM32::EQ);
2405 } 2406 }
2406 _br(Inst->getLabelDefault()); 2407 _br(Inst->getLabelDefault());
2407 } 2408 }
2408 2409
2409 void TargetARM32::lowerUnreachable(const InstUnreachable * /*Inst*/) { 2410 void TargetARM32::lowerUnreachable(const InstUnreachable * /*Inst*/) {
2410 _trap(); 2411 _trap();
2411 } 2412 }
2412 2413
2413 // Turn an i64 Phi instruction into a pair of i32 Phi instructions, to
2414 // preserve integrity of liveness analysis. Undef values are also
2415 // turned into zeroes, since loOperand() and hiOperand() don't expect
2416 // Undef input.
2417 void TargetARM32::prelowerPhis() { 2414 void TargetARM32::prelowerPhis() {
2418 UnimplementedError(Func->getContext()->getFlags()); 2415 PhiLowering::prelowerPhis32Bit<TargetARM32>(this, Context.getNode(), Func);
2419 } 2416 }
2420 2417
2421 // Lower the pre-ordered list of assignments into mov instructions. 2418 // Lower the pre-ordered list of assignments into mov instructions.
2422 // Also has to do some ad-hoc register allocation as necessary. 2419 // Also has to do some ad-hoc register allocation as necessary.
2423 void TargetARM32::lowerPhiAssignments(CfgNode *Node, 2420 void TargetARM32::lowerPhiAssignments(CfgNode *Node,
2424 const AssignList &Assignments) { 2421 const AssignList &Assignments) {
2425 (void)Node; 2422 (void)Node;
2426 (void)Assignments; 2423 (void)Assignments;
2427 UnimplementedError(Func->getContext()->getFlags()); 2424 UnimplementedError(Func->getContext()->getFlags());
2428 } 2425 }
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2767 << ".eabi_attribute 68, 1 @ Tag_Virtualization_use\n"; 2764 << ".eabi_attribute 68, 1 @ Tag_Virtualization_use\n";
2768 if (CPUFeatures.hasFeature(TargetARM32Features::HWDivArm)) { 2765 if (CPUFeatures.hasFeature(TargetARM32Features::HWDivArm)) {
2769 Str << ".eabi_attribute 44, 2 @ Tag_DIV_use\n"; 2766 Str << ".eabi_attribute 44, 2 @ Tag_DIV_use\n";
2770 } 2767 }
2771 // Technically R9 is used for TLS with Sandboxing, and we reserve it. 2768 // Technically R9 is used for TLS with Sandboxing, and we reserve it.
2772 // However, for compatibility with current NaCl LLVM, don't claim that. 2769 // However, for compatibility with current NaCl LLVM, don't claim that.
2773 Str << ".eabi_attribute 14, 3 @ Tag_ABI_PCS_R9_use: Not used\n"; 2770 Str << ".eabi_attribute 14, 3 @ Tag_ABI_PCS_R9_use: Not used\n";
2774 } 2771 }
2775 2772
2776 } // end of namespace Ice 2773 } // end of namespace Ice
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