ARM32: Lower more integer intrinsics and test.

src/IceInstARM32.h

 //===- subzero/src/IceInstARM32.h - ARM32 machine instructions --*- C++ -*-===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 244 matching lines @@
     k__Start = Inst::Target,
     Adc,
     Add,
     Adjuststack,
     And,
     Asr,
     Bic,
     Br,
     Call,
     Cmp,
+    Clz,
     Eor,
     Label,
     Ldr,
     Lsl,
     Lsr,
     Mla,
     Mls,
     Mov,
     Movt,
     Movw,
     Mul,
     Mvn,
     Orr,
     Pop,
     Push,
+    Rbit,
     Ret,
+    Rev,
     Rsb,
     Sbc,
     Sdiv,
     Str,
     Sub,
     Sxt,
     Trap,
     Tst,
     Udiv,
     Umull,
@@ skipping 26 matching lines @@
       : InstARM32(Func, Kind, Maxsrcs, Dest), Predicate(Predicate) {}
 
   CondARM32::Cond getPredicate() const { return Predicate; }
   void setPredicate(CondARM32::Cond Pred) { Predicate = Pred; }
 
   static const char *predString(CondARM32::Cond Predicate);
   void dumpOpcodePred(Ostream &Str, const char *Opcode, Type Ty) const;
 
   /// Shared emit routines for common forms of instructions.
   static void emitUnaryopGPR(const char *Opcode, const InstARM32Pred *Inst,
-                             const Cfg *Func);
+                             const Cfg *Func, bool NeedsWidthSuffix);
   static void emitTwoAddr(const char *Opcode, const InstARM32Pred *Inst,
                           const Cfg *Func);
   static void emitThreeAddr(const char *Opcode, const InstARM32Pred *Inst,
                             const Cfg *Func, bool SetFlags);
   static void emitFourAddr(const char *Opcode, const InstARM32Pred *Inst,
                            const Cfg *Func);
   static void emitCmpLike(const char *Opcode, const InstARM32Pred *Inst,
                           const Cfg *Func);
 
 protected:
   CondARM32::Cond Predicate;
 };
 
 template <typename StreamType>
 inline StreamType &operator<<(StreamType &Stream, CondARM32::Cond Predicate) {
   Stream << InstARM32Pred::predString(Predicate);
   return Stream;
 }
 
 /// Instructions of the form x := op(y).
-template <InstARM32::InstKindARM32 K>
+template <InstARM32::InstKindARM32 K, bool NeedsWidthSuffix>
 class InstARM32UnaryopGPR : public InstARM32Pred {
   InstARM32UnaryopGPR() = delete;
   InstARM32UnaryopGPR(const InstARM32UnaryopGPR &) = delete;
   InstARM32UnaryopGPR &operator=(const InstARM32UnaryopGPR &) = delete;
 
 public:
   static InstARM32UnaryopGPR *create(Cfg *Func, Variable *Dest, Operand *Src,
                                      CondARM32::Cond Predicate) {
     return new (Func->allocate<InstARM32UnaryopGPR>())
         InstARM32UnaryopGPR(Func, Dest, Src, Predicate);
   }
   void emit(const Cfg *Func) const override {
     if (!BuildDefs::dump())
       return;
-    emitUnaryopGPR(Opcode, this, Func);
+    emitUnaryopGPR(Opcode, this, Func, NeedsWidthSuffix);
   }
   void emitIAS(const Cfg *Func) const override {
     (void)Func;
     llvm_unreachable("Not yet implemented");
   }
   void dump(const Cfg *Func) const override {
     if (!BuildDefs::dump())
       return;
     Ostream &Str = Func->getContext()->getStrDump();
     dumpDest(Func);
@@ skipping 260 matching lines @@
 typedef InstARM32ThreeAddrGPR<InstARM32::Sdiv> InstARM32Sdiv;
 typedef InstARM32ThreeAddrGPR<InstARM32::Sub> InstARM32Sub;
 typedef InstARM32ThreeAddrGPR<InstARM32::Udiv> InstARM32Udiv;
 /// Move instruction (variable <- flex). This is more of a pseudo-inst.
 /// If var is a register, then we use "mov". If var is stack, then we use
 /// "str" to store to the stack.
 typedef InstARM32Movlike<InstARM32::Mov> InstARM32Mov;
 /// MovT leaves the bottom bits alone so dest is also a source.
 /// This helps indicate that a previous MovW setting dest is not dead code.
 typedef InstARM32TwoAddrGPR<InstARM32::Movt> InstARM32Movt;
-typedef InstARM32UnaryopGPR<InstARM32::Movw> InstARM32Movw;
-typedef InstARM32UnaryopGPR<InstARM32::Mvn> InstARM32Mvn;
+typedef InstARM32UnaryopGPR<InstARM32::Movw, false> InstARM32Movw;
+typedef InstARM32UnaryopGPR<InstARM32::Clz, false> InstARM32Clz;
+typedef InstARM32UnaryopGPR<InstARM32::Mvn, false> InstARM32Mvn;
+typedef InstARM32UnaryopGPR<InstARM32::Rbit, false> InstARM32Rbit;
+typedef InstARM32UnaryopGPR<InstARM32::Rev, false> InstARM32Rev;
 // Technically, the uxt{b,h} and sxt{b,h} instructions have a rotation
 // operand as well (rotate source by 8, 16, 24 bits prior to extending),
 // but we aren't using that for now, so just model as a Unaryop.
-typedef InstARM32UnaryopGPR<InstARM32::Sxt> InstARM32Sxt;
-typedef InstARM32UnaryopGPR<InstARM32::Uxt> InstARM32Uxt;
+typedef InstARM32UnaryopGPR<InstARM32::Sxt, true> InstARM32Sxt;
+typedef InstARM32UnaryopGPR<InstARM32::Uxt, true> InstARM32Uxt;
 typedef InstARM32FourAddrGPR<InstARM32::Mla> InstARM32Mla;
 typedef InstARM32FourAddrGPR<InstARM32::Mls> InstARM32Mls;
 typedef InstARM32CmpLike<InstARM32::Cmp> InstARM32Cmp;
 typedef InstARM32CmpLike<InstARM32::Tst> InstARM32Tst;
 
 // InstARM32Label represents an intra-block label that is the target
 // of an intra-block branch.  The offset between the label and the
 // branch must be fit in the instruction immediate (considered "near").
 class InstARM32Label : public InstARM32 {
   InstARM32Label() = delete;
@@ skipping 305 matching lines @@
 // Declare partial template specializations of emit() methods that
 // already have default implementations.  Without this, there is the
 // possibility of ODR violations and link errors.
 
 template <> void InstARM32Movw::emit(const Cfg *Func) const;
 template <> void InstARM32Movt::emit(const Cfg *Func) const;
 
 } // end of namespace Ice
 
 #endif // SUBZERO_SRC_ICEINSTARM32_H