MIPS: disabling rsqrt and recip for mips32r1

src/mips/simulator-mips.cc

Index: src/mips/simulator-mips.cc
diff --git a/src/mips/simulator-mips.cc b/src/mips/simulator-mips.cc
index dfd440fcbbc1608da2bda589cd674e619ae6045e..83b5905cd0de688556545ed4f7b6ac0ed3398422 100644
--- a/src/mips/simulator-mips.cc
+++ b/src/mips/simulator-mips.cc
@@ -2711,11 +2711,13 @@ void Simulator::DecodeTypeRegisterDRsType(Instruction* instr,
       set_fpu_register_double(fd_reg, fast_sqrt(fs));
       break;
     case RSQRT_D: {
+      DCHECK(IsMipsArchVariant(kMips32r2) || IsMipsArchVariant(kMips32r6));
       double result = 1.0 / fast_sqrt(fs);
       set_fpu_register_double(fd_reg, result);
       break;
     }
     case RECIP_D: {
+      DCHECK(IsMipsArchVariant(kMips32r2) || IsMipsArchVariant(kMips32r6));
       double result = 1.0 / fs;
       set_fpu_register_double(fd_reg, result);
       break;
@@ -3117,11 +3119,13 @@ void Simulator::DecodeTypeRegisterSRsType(Instruction* instr,
       set_fpu_register_float(fd_reg, fast_sqrt(fs));
       break;
     case RSQRT_S: {
+      DCHECK(IsMipsArchVariant(kMips32r2) || IsMipsArchVariant(kMips32r6));
       float result = 1.0 / fast_sqrt(fs);
       set_fpu_register_float(fd_reg, result);
       break;
     }
     case RECIP_S: {
+      DCHECK(IsMipsArchVariant(kMips32r2) || IsMipsArchVariant(kMips32r6));
       float result = 1.0 / fs;
       set_fpu_register_float(fd_reg, result);
       break;