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Issue 1221663006: MIPS: disabling rsqrt and recip for mips32r1 (Closed) Base URL: https://chromium.googlesource.com/v8/v8.git@master
Patch Set: Created 5 years, 5 months ago
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1 // Copyright 2011 the V8 project authors. All rights reserved. 1 // Copyright 2011 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be 2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file. 3 // found in the LICENSE file.
4 4
5 #include <limits.h> 5 #include <limits.h>
6 #include <stdarg.h> 6 #include <stdarg.h>
7 #include <stdlib.h> 7 #include <stdlib.h>
8 #include <cmath> 8 #include <cmath>
9 9
10 #include "src/v8.h" 10 #include "src/v8.h"
(...skipping 2693 matching lines...) Expand 10 before | Expand all | Expand 10 after
2704 case MOV_D: 2704 case MOV_D:
2705 set_fpu_register_double(fd_reg, fs); 2705 set_fpu_register_double(fd_reg, fs);
2706 break; 2706 break;
2707 case NEG_D: 2707 case NEG_D:
2708 set_fpu_register_double(fd_reg, -fs); 2708 set_fpu_register_double(fd_reg, -fs);
2709 break; 2709 break;
2710 case SQRT_D: 2710 case SQRT_D:
2711 set_fpu_register_double(fd_reg, fast_sqrt(fs)); 2711 set_fpu_register_double(fd_reg, fast_sqrt(fs));
2712 break; 2712 break;
2713 case RSQRT_D: { 2713 case RSQRT_D: {
2714 DCHECK(IsMipsArchVariant(kMips32r2) || IsMipsArchVariant(kMips32r6));
2714 double result = 1.0 / fast_sqrt(fs); 2715 double result = 1.0 / fast_sqrt(fs);
2715 set_fpu_register_double(fd_reg, result); 2716 set_fpu_register_double(fd_reg, result);
2716 break; 2717 break;
2717 } 2718 }
2718 case RECIP_D: { 2719 case RECIP_D: {
2720 DCHECK(IsMipsArchVariant(kMips32r2) || IsMipsArchVariant(kMips32r6));
2719 double result = 1.0 / fs; 2721 double result = 1.0 / fs;
2720 set_fpu_register_double(fd_reg, result); 2722 set_fpu_register_double(fd_reg, result);
2721 break; 2723 break;
2722 } 2724 }
2723 case C_UN_D: 2725 case C_UN_D:
2724 set_fcsr_bit(fcsr_cc, std::isnan(fs) || std::isnan(ft)); 2726 set_fcsr_bit(fcsr_cc, std::isnan(fs) || std::isnan(ft));
2725 break; 2727 break;
2726 case C_EQ_D: 2728 case C_EQ_D:
2727 set_fcsr_bit(fcsr_cc, (fs == ft)); 2729 set_fcsr_bit(fcsr_cc, (fs == ft));
2728 break; 2730 break;
(...skipping 381 matching lines...) Expand 10 before | Expand all | Expand 10 after
3110 case MOV_S: 3112 case MOV_S:
3111 set_fpu_register_float(fd_reg, fs); 3113 set_fpu_register_float(fd_reg, fs);
3112 break; 3114 break;
3113 case NEG_S: 3115 case NEG_S:
3114 set_fpu_register_float(fd_reg, -fs); 3116 set_fpu_register_float(fd_reg, -fs);
3115 break; 3117 break;
3116 case SQRT_S: 3118 case SQRT_S:
3117 set_fpu_register_float(fd_reg, fast_sqrt(fs)); 3119 set_fpu_register_float(fd_reg, fast_sqrt(fs));
3118 break; 3120 break;
3119 case RSQRT_S: { 3121 case RSQRT_S: {
3122 DCHECK(IsMipsArchVariant(kMips32r2) || IsMipsArchVariant(kMips32r6));
3120 float result = 1.0 / fast_sqrt(fs); 3123 float result = 1.0 / fast_sqrt(fs);
3121 set_fpu_register_float(fd_reg, result); 3124 set_fpu_register_float(fd_reg, result);
3122 break; 3125 break;
3123 } 3126 }
3124 case RECIP_S: { 3127 case RECIP_S: {
3128 DCHECK(IsMipsArchVariant(kMips32r2) || IsMipsArchVariant(kMips32r6));
3125 float result = 1.0 / fs; 3129 float result = 1.0 / fs;
3126 set_fpu_register_float(fd_reg, result); 3130 set_fpu_register_float(fd_reg, result);
3127 break; 3131 break;
3128 } 3132 }
3129 case C_F_D: 3133 case C_F_D:
3130 set_fcsr_bit(fcsr_cc, false); 3134 set_fcsr_bit(fcsr_cc, false);
3131 break; 3135 break;
3132 case C_UN_D: 3136 case C_UN_D:
3133 set_fcsr_bit(fcsr_cc, std::isnan(fs) || std::isnan(ft)); 3137 set_fcsr_bit(fcsr_cc, std::isnan(fs) || std::isnan(ft));
3134 break; 3138 break;
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4607 4611
4608 4612
4609 #undef UNSUPPORTED 4613 #undef UNSUPPORTED
4610 4614
4611 } // namespace internal 4615 } // namespace internal
4612 } // namespace v8 4616 } // namespace v8
4613 4617
4614 #endif // USE_SIMULATOR 4618 #endif // USE_SIMULATOR
4615 4619
4616 #endif // V8_TARGET_ARCH_MIPS 4620 #endif // V8_TARGET_ARCH_MIPS
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