Subzero: Add -Wshadow to the build.

src/IceInstARM32.cpp

 //===- subzero/src/IceInstARM32.cpp - ARM32 instruction implementation ----===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file implements the InstARM32 and OperandARM32 classes,
@@ skipping 135 matching lines @@
   if (!BuildDefs::dump())
     return;
   Ostream &Str = Func->getContext()->getStrEmit();
   assert(Inst->getSrcSize() == 2);
   Str << "\t" << Opcode << Inst->getPredicate() << "\t";
   Inst->getSrc(0)->emit(Func);
   Str << ", ";
   Inst->getSrc(1)->emit(Func);
 }
 
-OperandARM32Mem::OperandARM32Mem(Cfg * /* Func */, Type Ty, Variable *Base,
-                                 ConstantInteger32 *ImmOffset, AddrMode Mode)
-    : OperandARM32(kMem, Ty), Base(Base), ImmOffset(ImmOffset), Index(nullptr),
-      ShiftOp(kNoShift), ShiftAmt(0), Mode(Mode) {
+OperandARM32Mem::OperandARM32Mem(Cfg * /* Func */, Type Ty, Variable *MyBase,
+                                 ConstantInteger32 *MyImmOffset,
+                                 AddrMode MyMode)
+    : OperandARM32(kMem, Ty), Base(MyBase), ImmOffset(MyImmOffset),
+      Index(nullptr), ShiftOp(kNoShift), ShiftAmt(0), Mode(MyMode) {
   // The Neg modes are only needed for Reg +/- Reg.
   assert(!isNegAddrMode());
   NumVars = 1;
   Vars = &this->Base;
 }
 
-OperandARM32Mem::OperandARM32Mem(Cfg *Func, Type Ty, Variable *Base,
-                                 Variable *Index, ShiftKind ShiftOp,
-                                 uint16_t ShiftAmt, AddrMode Mode)
-    : OperandARM32(kMem, Ty), Base(Base), ImmOffset(0), Index(Index),
-      ShiftOp(ShiftOp), ShiftAmt(ShiftAmt), Mode(Mode) {
+OperandARM32Mem::OperandARM32Mem(Cfg *Func, Type Ty, Variable *MyBase,
+                                 Variable *MyIndex, ShiftKind MyShiftOp,
+                                 uint16_t MyShiftAmt, AddrMode MyMode)
+    : OperandARM32(kMem, Ty), Base(MyBase), ImmOffset(0), Index(MyIndex),
+      ShiftOp(MyShiftOp), ShiftAmt(MyShiftAmt), Mode(MyMode) {
   NumVars = 2;
   Vars = Func->allocateArrayOf<Variable *>(2);
   Vars[0] = Base;
   Vars[1] = Index;
 }
 
 bool OperandARM32Mem::canHoldOffset(Type Ty, bool SignExt, int32_t Offset) {
   int32_t Bits = SignExt ? TypeARM32Attributes[Ty].SExtAddrOffsetBits
                          : TypeARM32Attributes[Ty].ZExtAddrOffsetBits;
   if (Bits == 0)
     return Offset == 0;
   // Note that encodings for offsets are sign-magnitude for ARM, so we check
   // with IsAbsoluteUint().
   if (isScalarFloatingType(Ty))
     return Utils::IsAligned(Offset, 4) && Utils::IsAbsoluteUint(Bits, Offset);
   return Utils::IsAbsoluteUint(Bits, Offset);
 }
 
 OperandARM32FlexImm::OperandARM32FlexImm(Cfg * /* Func */, Type Ty,
-                                         uint32_t Imm, uint32_t RotateAmt)
-    : OperandARM32Flex(kFlexImm, Ty), Imm(Imm), RotateAmt(RotateAmt) {
+                                         uint32_t MyImm, uint32_t MyRotateAmt)
+    : OperandARM32Flex(kFlexImm, Ty), Imm(MyImm), RotateAmt(MyRotateAmt) {
   NumVars = 0;
   Vars = nullptr;
 }
 
 bool OperandARM32FlexImm::canHoldImm(uint32_t Immediate, uint32_t *RotateAmt,
                                      uint32_t *Immed_8) {
   // Avoid the more expensive test for frequent small immediate values.
   if (Immediate <= 0xFF) {
     *RotateAmt = 0;
     *Immed_8 = Immediate;
     return true;
   }
   // Note that immediate must be unsigned for the test to work correctly.
   for (int Rot = 1; Rot < 16; Rot++) {
     uint32_t Imm8 = Utils::rotateLeft32(Immediate, 2 * Rot);
     if (Imm8 <= 0xFF) {
       *RotateAmt = Rot;
       *Immed_8 = Imm8;
       return true;
     }
   }
   return false;
 }
 
-OperandARM32FlexReg::OperandARM32FlexReg(Cfg *Func, Type Ty, Variable *Reg,
-                                         ShiftKind ShiftOp, Operand *ShiftAmt)
-    : OperandARM32Flex(kFlexReg, Ty), Reg(Reg), ShiftOp(ShiftOp),
-      ShiftAmt(ShiftAmt) {
+OperandARM32FlexReg::OperandARM32FlexReg(Cfg *Func, Type Ty, Variable *MyReg,
+                                         ShiftKind MyShiftOp,
+                                         Operand *MyShiftAmt)
+    : OperandARM32Flex(kFlexReg, Ty), Reg(MyReg), ShiftOp(MyShiftOp),
+      ShiftAmt(MyShiftAmt) {
   NumVars = 1;
   Variable *ShiftVar = llvm::dyn_cast_or_null<Variable>(ShiftAmt);
   if (ShiftVar)
     ++NumVars;
   Vars = Func->allocateArrayOf<Variable *>(NumVars);
   Vars[0] = Reg;
   if (ShiftVar)
     Vars[1] = ShiftVar;
 }
 
 InstARM32AdjustStack::InstARM32AdjustStack(Cfg *Func, Variable *SP,
-                                           SizeT Amount, Operand *SrcAmount)
-    : InstARM32(Func, InstARM32::Adjuststack, 2, SP), Amount(Amount) {
+                                           SizeT MyAmount, Operand *SrcAmount)
+    : InstARM32(Func, InstARM32::Adjuststack, 2, SP), Amount(MyAmount) {
   addSource(SP);
   addSource(SrcAmount);
 }
 
-InstARM32Br::InstARM32Br(Cfg *Func, const CfgNode *TargetTrue,
-                         const CfgNode *TargetFalse,
-                         const InstARM32Label *Label, CondARM32::Cond Pred)
+InstARM32Br::InstARM32Br(Cfg *Func, const CfgNode *MyTargetTrue,
+                         const CfgNode *MyTargetFalse,
+                         const InstARM32Label *MyLabel, CondARM32::Cond Pred)
     : InstARM32Pred(Func, InstARM32::Br, 0, nullptr, Pred),
-      TargetTrue(TargetTrue), TargetFalse(TargetFalse), Label(Label) {}
+      TargetTrue(MyTargetTrue), TargetFalse(MyTargetFalse), Label(MyLabel) {}
 
 bool InstARM32Br::optimizeBranch(const CfgNode *NextNode) {
   // If there is no next block, then there can be no fallthrough to
   // optimize.
   if (NextNode == nullptr)
     return false;
   // Intra-block conditional branches can't be optimized.
   if (Label)
     return false;
   // If there is no fallthrough node, such as a non-default case label
@@ skipping 51 matching lines @@
 IceString InstARM32Label::getName(const Cfg *Func) const {
   return ".L" + Func->getFunctionName() + "$local$__" + std::to_string(Number);
 }
 
 InstARM32Ldr::InstARM32Ldr(Cfg *Func, Variable *Dest, OperandARM32Mem *Mem,
                            CondARM32::Cond Predicate)
     : InstARM32Pred(Func, InstARM32::Ldr, 1, Dest, Predicate) {
   addSource(Mem);
 }
 
-InstARM32Pop::InstARM32Pop(Cfg *Func, const VarList &Dests)
-    : InstARM32(Func, InstARM32::Pop, 0, nullptr), Dests(Dests) {
+InstARM32Pop::InstARM32Pop(Cfg *Func, const VarList &MyDests)
+    : InstARM32(Func, InstARM32::Pop, 0, nullptr), Dests(MyDests) {
   // Track modifications to Dests separately via FakeDefs.
   // Also, a pop instruction affects the stack pointer and so it should not
   // be allowed to be automatically dead-code eliminated. This is automatic
   // since we leave the Dest as nullptr.
 }
 
 InstARM32Push::InstARM32Push(Cfg *Func, const VarList &Srcs)
     : InstARM32(Func, InstARM32::Push, Srcs.size(), nullptr) {
   for (Variable *Source : Srcs)
     addSource(Source);
 }
 
 InstARM32Ret::InstARM32Ret(Cfg *Func, Variable *LR, Variable *Source)
     : InstARM32(Func, InstARM32::Ret, Source ? 2 : 1, nullptr) {
   addSource(LR);
   if (Source)
     addSource(Source);
 }
 
 InstARM32Str::InstARM32Str(Cfg *Func, Variable *Value, OperandARM32Mem *Mem,
                            CondARM32::Cond Predicate)
     : InstARM32Pred(Func, InstARM32::Str, 2, nullptr, Predicate) {
   addSource(Value);
   addSource(Mem);
 }
 
 InstARM32Trap::InstARM32Trap(Cfg *Func)
     : InstARM32(Func, InstARM32::Trap, 0, nullptr) {}
 
-InstARM32Umull::InstARM32Umull(Cfg *Func, Variable *DestLo, Variable *DestHi,
+InstARM32Umull::InstARM32Umull(Cfg *Func, Variable *DestLo, Variable *MyDestHi,
                                Variable *Src0, Variable *Src1,
                                CondARM32::Cond Predicate)
     : InstARM32Pred(Func, InstARM32::Umull, 2, DestLo, Predicate),
       // DestHi is expected to have a FakeDef inserted by the lowering code.
-      DestHi(DestHi) {
+      DestHi(MyDestHi) {
   addSource(Src0);
   addSource(Src1);
 }
 
 // ======================== Dump routines ======================== //
 
 // Two-addr ops
 template <> const char *InstARM32Movt::Opcode = "movt";
 // Unary ops
 template <> const char *InstARM32Movw::Opcode = "movw";
@@ skipping 33 matching lines @@
   Inst::dump(Func);
 }
 
 template <> void InstARM32Mov::emit(const Cfg *Func) const {
   if (!BuildDefs::dump())
     return;
   Ostream &Str = Func->getContext()->getStrEmit();
   assert(getSrcSize() == 1);
   Variable *Dest = getDest();
   if (Dest->hasReg()) {
-    IceString Opcode = "mov";
+    IceString MyOpcode = "mov";
     Operand *Src0 = getSrc(0);
     if (const auto *Src0V = llvm::dyn_cast<Variable>(Src0)) {
       if (!Src0V->hasReg()) {
-        Opcode = IceString("ldr"); // Always use the whole stack slot.
+        MyOpcode = IceString("ldr"); // Always use the whole stack slot.
       }
     } else {
       if (llvm::isa<OperandARM32Mem>(Src0))
-        Opcode = IceString("ldr") + getWidthString(Dest->getType());
+        MyOpcode = IceString("ldr") + getWidthString(Dest->getType());
     }
-    Str << "\t" << Opcode << getPredicate() << "\t";
+    Str << "\t" << MyOpcode << getPredicate() << "\t";
     getDest()->emit(Func);
     Str << ", ";
     getSrc(0)->emit(Func);
   } else {
     Variable *Src0 = llvm::cast<Variable>(getSrc(0));
     assert(Src0->hasReg());
     Str << "\t"
         << "str" << getPredicate() << "\t";
     Src0->emit(Func);
     Str << ", ";
@@ skipping 464 matching lines @@
   } else {
     getOffset()->dump(Func, Str);
   }
   Str << "] AddrMode==" << getAddrMode();
 }
 
 void OperandARM32FlexImm::emit(const Cfg *Func) const {
   if (!BuildDefs::dump())
     return;
   Ostream &Str = Func->getContext()->getStrEmit();
-  uint32_t Imm = getImm();
-  uint32_t RotateAmt = getRotateAmt();
-  Str << "#" << Utils::rotateRight32(Imm, 2 * RotateAmt);
+  Str << "#" << Utils::rotateRight32(getImm(), 2 * getRotateAmt());
 }
 
 void OperandARM32FlexImm::dump(const Cfg * /* Func */, Ostream &Str) const {
   if (!BuildDefs::dump())
     return;
-  uint32_t Imm = getImm();
-  uint32_t RotateAmt = getRotateAmt();
-  Str << "#(" << Imm << " ror 2*" << RotateAmt << ")";
+  Str << "#(" << getImm() << " ror 2*" << getRotateAmt() << ")";
 }
 
 void OperandARM32FlexReg::emit(const Cfg *Func) const {
   if (!BuildDefs::dump())
     return;
   Ostream &Str = Func->getContext()->getStrEmit();
   getReg()->emit(Func);
   if (getShiftOp() != kNoShift) {
     Str << ", " << InstARM32ShiftAttributes[getShiftOp()].EmitString << " ";
     getShiftAmt()->emit(Func);
   }
 }
 
 void OperandARM32FlexReg::dump(const Cfg *Func, Ostream &Str) const {
   if (!BuildDefs::dump())
     return;
-  Variable *Reg = getReg();
   if (Func)
     Reg->dump(Func);
   else
     Reg->dump(Str);
   if (getShiftOp() != kNoShift) {
     Str << ", " << InstARM32ShiftAttributes[getShiftOp()].EmitString << " ";
     if (Func)
       getShiftAmt()->dump(Func);
     else
       getShiftAmt()->dump(Str);
   }
 }
 
 } // end of namespace Ice