Changes the TargetX8632 to inherit from TargetX86Base<TargetX8632>.

src/IceTargetLoweringX86BaseImpl.h

 //===- subzero/src/IceTargetLoweringX86BaseImpl.h - x86 lowering -*- C++ -*-==//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 246 matching lines @@
 }
 
 template <class Machine>
 void TargetX86Base<Machine>::initNodeForLowering(CfgNode *Node) {
   FoldingInfo.init(Node);
   FoldingInfo.dump(Func);
 }
 
 template <class Machine>
 TargetX86Base<Machine>::TargetX86Base(Cfg *Func)
-    : Machine(Func) {
+    : TargetLowering(Func) {
   static_assert(
       (Traits::InstructionSet::End - Traits::InstructionSet::Begin) ==
           (TargetInstructionSet::X86InstructionSet_End -
            TargetInstructionSet::X86InstructionSet_Begin),
       "Traits::InstructionSet range different from TargetInstructionSet");
   if (Func->getContext()->getFlags().getTargetInstructionSet() !=
       TargetInstructionSet::BaseInstructionSet) {
     InstructionSet = static_cast<typename Traits::InstructionSet>(
         (Func->getContext()->getFlags().getTargetInstructionSet() -
          TargetInstructionSet::X86InstructionSet_Begin) +
@@ skipping 167 matching lines @@
   if (Func->hasError())
     return;
   Func->dump("After stack frame mapping");
 
   // Nop insertion
   if (Ctx->getFlags().shouldDoNopInsertion()) {
     Func->doNopInsertion();
   }
 }
 
-bool canRMW(const InstArithmetic *Arith) {
+inline bool canRMW(const InstArithmetic *Arith) {

[John, 2015/07/08 16:37:40]

the lack of "inline" here was causing (as expected) multiple definition errors.
The previous implementation only ever included this file once, so everything was
fine. To be fair, I was expecting these errors to show up once the TargetX8664
was introduced.

Alternatively, I could turn all these new "inline" methods into template <class
Machine> so that "inline" is no longer needed. There should be no difference
between the two versions in the release binary.

   Type Ty = Arith->getDest()->getType();
   // X86 vector instructions write to a register and have no RMW option.
   if (isVectorType(Ty))
     return false;
   bool isI64 = Ty == IceType_i64;
 
   switch (Arith->getOp()) {
   // Not handled for lack of simple lowering:
   //   shift on i64
   //   mul, udiv, urem, sdiv, srem, frem
@@ skipping 103 matching lines @@
               continue;
             if (Func->isVerbose(IceV_RMW)) {
               Str << "Found RMW in " << Func->getFunctionName() << ":\n  ";
               Load->dump(Func);
               Str << "\n  ";
               Arith->dump(Func);
               Str << "\n  ";
               Store->dump(Func);
               Str << "\n";
             }
-            Variable *Beacon = Func->template makeVariable(IceType_i32);
+            Variable *Beacon = Func-> makeVariable(IceType_i32);
             Beacon->setWeight(0);
             Store->setRmwBeacon(Beacon);
             InstFakeDef *BeaconDef = InstFakeDef::create(Func, Beacon);
             Node->getInsts().insert(I3, BeaconDef);
             auto *RMW = Traits::Insts::FakeRMW::create(
                 Func, ArithSrcOther, Store->getAddr(), Beacon, Arith->getOp());
             Node->getInsts().insert(I3, RMW);
           }
         }
       }
     }
   }
 }
 
 // Converts a ConstantInteger32 operand into its constant value, or
 // MemoryOrderInvalid if the operand is not a ConstantInteger32.
-uint64_t getConstantMemoryOrder(Operand *Opnd) {
+inline uint64_t getConstantMemoryOrder(Operand *Opnd) {
   if (auto Integer = llvm::dyn_cast<ConstantInteger32>(Opnd))
     return Integer->getValue();
   return Intrinsics::MemoryOrderInvalid;
 }
 
 /// Determines whether the dest of a Load instruction can be folded
 /// into one of the src operands of a 2-operand instruction.  This is
 /// true as long as the load dest matches exactly one of the binary
 /// instruction's src operands.  Replaces Src0 or Src1 with LoadSrc if
 /// the answer is true.
-bool canFoldLoadIntoBinaryInst(Operand *LoadSrc, Variable *LoadDest,
-                               Operand *&Src0, Operand *&Src1) {
+inline bool canFoldLoadIntoBinaryInst(Operand *LoadSrc, Variable *LoadDest,
+                                      Operand *&Src0, Operand *&Src1) {
   if (Src0 == LoadDest && Src1 != LoadDest) {
     Src0 = LoadSrc;
     return true;
   }
   if (Src0 != LoadDest && Src1 == LoadDest) {
     Src1 = LoadSrc;
     return true;
   }
   return false;
 }
@@ skipping 98 matching lines @@
 
 template <class Machine>
 Variable *TargetX86Base<Machine>::getPhysicalRegister(SizeT RegNum, Type Ty) {
   if (Ty == IceType_void)
     Ty = IceType_i32;
   if (PhysicalRegisters[Ty].empty())
     PhysicalRegisters[Ty].resize(Traits::RegisterSet::Reg_NUM);
   assert(RegNum < PhysicalRegisters[Ty].size());
   Variable *Reg = PhysicalRegisters[Ty][RegNum];
   if (Reg == nullptr) {
-    Reg = Func->template makeVariable(Ty);
+    Reg = Func-> makeVariable(Ty);
     Reg->setRegNum(RegNum);
     PhysicalRegisters[Ty][RegNum] = Reg;
     // Specially mark esp as an "argument" so that it is considered
     // live upon function entry.
     if (RegNum == Traits::RegisterSet::Reg_esp) {
       Func->addImplicitArg(Reg);
       Reg->setIgnoreLiveness();
     }
   }
   return Reg;
@@ skipping 52 matching lines @@
        I < E && NumXmmArgs < Traits::X86_MAX_XMM_ARGS; ++I) {
     Variable *Arg = Args[I];
     Type Ty = Arg->getType();
     if (!isVectorType(Ty))
       continue;
     // Replace Arg in the argument list with the home register.  Then
     // generate an instruction in the prolog to copy the home register
     // to the assigned location of Arg.
     int32_t RegNum = Traits::RegisterSet::Reg_xmm0 + NumXmmArgs;
     ++NumXmmArgs;
-    Variable *RegisterArg = Func->template makeVariable(Ty);
+    Variable *RegisterArg = Func-> makeVariable(Ty);
     if (BuildDefs::dump())
       RegisterArg->setName(Func, "home_reg:" + Arg->getName(Func));
     RegisterArg->setRegNum(RegNum);
     RegisterArg->setIsArg();
     Arg->setIsArg(false);
 
     Args[I] = RegisterArg;
     Context.insert(InstAssign::create(Func, Arg, RegisterArg));
   }
 }
@@ skipping 295 matching lines @@
   if (!Ctx->getFlags().getUseSandboxing())
     return;
   // Change the original ret instruction into a sandboxed return sequence.
   // t:ecx = pop
   // bundle_lock
   // and t, ~31
   // jmp *t
   // bundle_unlock
   // FakeUse <original_ret_operand>
   const SizeT BundleSize =
-      1 << Func->template getAssembler<>()->getBundleAlignLog2Bytes();
+      1 << Func-> getAssembler<>()->getBundleAlignLog2Bytes();
   Variable *T_ecx = makeReg(IceType_i32, Traits::RegisterSet::Reg_ecx);
   _pop(T_ecx);
   _bundle_lock();
   _and(T_ecx, Ctx->getConstantInt32(~(BundleSize - 1)));
   _jmp(T_ecx);
   _bundle_unlock();
   if (RI->getSrcSize()) {
     Variable *RetValue = llvm::cast<Variable>(RI->getSrc(0));
     Context.insert(InstFakeUse::create(Func, RetValue));
   }
@@ skipping 11 matching lines @@
   case IceType_f64:
     break;
   }
   Variable *Lo = Var->getLo();
   Variable *Hi = Var->getHi();
   if (Lo) {
     assert(Hi);
     return;
   }
   assert(Hi == nullptr);
-  Lo = Func->template makeVariable(IceType_i32);
-  Hi = Func->template makeVariable(IceType_i32);
+  Lo = Func-> makeVariable(IceType_i32);
+  Hi = Func-> makeVariable(IceType_i32);
   if (BuildDefs::dump()) {
     Lo->setName(Func, Var->getName(Func) + "__lo");
     Hi->setName(Func, Var->getName(Func) + "__hi");
   }
   Var->setLoHi(Lo, Hi);
   if (Var->getIsArg()) {
     Lo->setIsArg();
     Hi->setIsArg();
   }
 }
@@ skipping 1072 matching lines @@
   Operand *CallTarget = legalize(Instr->getCallTarget());
   const bool NeedSandboxing = Ctx->getFlags().getUseSandboxing();
   if (NeedSandboxing) {
     if (llvm::isa<Constant>(CallTarget)) {
       _bundle_lock(InstBundleLock::Opt_AlignToEnd);
     } else {
       Variable *CallTargetVar = nullptr;
       _mov(CallTargetVar, CallTarget);
       _bundle_lock(InstBundleLock::Opt_AlignToEnd);
       const SizeT BundleSize =
-          1 << Func->template getAssembler<>()->getBundleAlignLog2Bytes();
+          1 << Func-> getAssembler<>()->getBundleAlignLog2Bytes();
       _and(CallTargetVar, Ctx->getConstantInt32(~(BundleSize - 1)));
       CallTarget = CallTargetVar;
     }
   }
   Inst *NewCall = Traits::Insts::Call::create(Func, ReturnReg, CallTarget);
   Context.insert(NewCall);
   if (NeedSandboxing)
     _bundle_unlock();
   if (ReturnRegHi)
     Context.insert(InstFakeDef::create(Func, ReturnRegHi));
@@ skipping 408 matching lines @@
       assert((DestType == IceType_i32 && SrcType == IceType_f32) ||
              (DestType == IceType_f32 && SrcType == IceType_i32));
       // a.i32 = bitcast b.f32 ==>
       //   t.f32 = b.f32
       //   s.f32 = spill t.f32
       //   a.i32 = s.f32
       Variable *T = nullptr;
       // TODO: Should be able to force a spill setup by calling legalize() with
       // Legal_Mem and not Legal_Reg or Legal_Imm.
       typename Traits::SpillVariable *SpillVar =
-          Func->template makeVariable<typename Traits::SpillVariable>(SrcType);
+          Func-> makeVariable<typename Traits::SpillVariable>(SrcType);
       SpillVar->setLinkedTo(Dest);
       Variable *Spill = SpillVar;
       Spill->setWeight(RegWeight::Zero);
       _mov(T, Src0RM);
       _mov(Spill, T);
       _mov(Dest, Spill);
     } break;
     case IceType_i64: {
       Operand *Src0RM = legalize(Src0, Legal_Reg | Legal_Mem);
       assert(Src0RM->getType() == IceType_f64);
       // a.i64 = bitcast b.f64 ==>
       //   s.f64 = spill b.f64
       //   t_lo.i32 = lo(s.f64)
       //   a_lo.i32 = t_lo.i32
       //   t_hi.i32 = hi(s.f64)
       //   a_hi.i32 = t_hi.i32
       Operand *SpillLo, *SpillHi;
       if (auto *Src0Var = llvm::dyn_cast<Variable>(Src0RM)) {
         typename Traits::SpillVariable *SpillVar =
-            Func->template makeVariable<typename Traits::SpillVariable>(
+            Func-> makeVariable<typename Traits::SpillVariable>(
                 IceType_f64);
         SpillVar->setLinkedTo(Src0Var);
         Variable *Spill = SpillVar;
         Spill->setWeight(RegWeight::Zero);
         _movq(Spill, Src0RM);
         SpillLo = Traits::VariableSplit::create(Func, Spill,
                                                 Traits::VariableSplit::Low);
         SpillHi = Traits::VariableSplit::create(Func, Spill,
                                                 Traits::VariableSplit::High);
       } else {
         SpillLo = loOperand(Src0RM);
         SpillHi = hiOperand(Src0RM);
       }
 
       Variable *DestLo = llvm::cast<Variable>(loOperand(Dest));
       Variable *DestHi = llvm::cast<Variable>(hiOperand(Dest));
       Variable *T_Lo = makeReg(IceType_i32);
       Variable *T_Hi = makeReg(IceType_i32);
 
       _mov(T_Lo, SpillLo);
       _mov(DestLo, T_Lo);
       _mov(T_Hi, SpillHi);
       _mov(DestHi, T_Hi);
     } break;
     case IceType_f64: {
       Src0 = legalize(Src0);
       assert(Src0->getType() == IceType_i64);
       if (llvm::isa<typename Traits::X86OperandMem>(Src0)) {
-        Variable *T = Func->template makeVariable(Dest->getType());
+        Variable *T = Func-> makeVariable(Dest->getType());
         _movq(T, Src0);
         _movq(Dest, T);
         break;
       }
       // a.f64 = bitcast b.i64 ==>
       //   t_lo.i32 = b_lo.i32
       //   FakeDef(s.f64)
       //   lo(s.f64) = t_lo.i32
       //   t_hi.i32 = b_hi.i32
       //   hi(s.f64) = t_hi.i32
       //   a.f64 = s.f64
       typename Traits::SpillVariable *SpillVar =
-          Func->template makeVariable<typename Traits::SpillVariable>(
+          Func-> makeVariable<typename Traits::SpillVariable>(
               IceType_f64);
       SpillVar->setLinkedTo(Dest);
       Variable *Spill = SpillVar;
       Spill->setWeight(RegWeight::Zero);
 
       Variable *T_Lo = nullptr, *T_Hi = nullptr;
       typename Traits::VariableSplit *SpillLo = Traits::VariableSplit::create(
           Func, Spill, Traits::VariableSplit::Low);
       typename Traits::VariableSplit *SpillHi = Traits::VariableSplit::create(
           Func, Spill, Traits::VariableSplit::High);
       _mov(T_Lo, loOperand(Src0));
       // Technically, the Spill is defined after the _store happens, but
       // SpillLo is considered a "use" of Spill so define Spill before it
       // is used.
       Context.insert(InstFakeDef::create(Func, Spill));
       _store(T_Lo, SpillLo);
       _mov(T_Hi, hiOperand(Src0));
       _store(T_Hi, SpillHi);
       _movq(Dest, Spill);
     } break;
     case IceType_v8i1: {
       assert(Src0->getType() == IceType_i8);
       InstCall *Call = makeHelperCall(H_bitcast_i8_8xi1, Dest, 1);
-      Variable *Src0AsI32 = Func->template makeVariable(stackSlotType());
+      Variable *Src0AsI32 = Func-> makeVariable(stackSlotType());
       // Arguments to functions are required to be at least 32 bits wide.
       lowerCast(InstCast::create(Func, InstCast::Zext, Src0AsI32, Src0));
       Call->addArg(Src0AsI32);
       lowerCall(Call);
     } break;
     case IceType_v16i1: {
       assert(Src0->getType() == IceType_i16);
       InstCall *Call = makeHelperCall(H_bitcast_i16_16xi1, Dest, 1);
-      Variable *Src0AsI32 = Func->template makeVariable(stackSlotType());
+      Variable *Src0AsI32 = Func-> makeVariable(stackSlotType());
       // Arguments to functions are required to be at least 32 bits wide.
       lowerCast(InstCast::create(Func, InstCast::Zext, Src0AsI32, Src0));
       Call->addArg(Src0AsI32);
       lowerCall(Call);
     } break;
     case IceType_v8i16:
     case IceType_v16i8:
     case IceType_v4i32:
     case IceType_v4f32: {
       _movp(Dest, legalizeToVar(Src0));
@@ skipping 50 matching lines @@
       // keep the live range analysis consistent.
       Context.insert(InstFakeDef::create(Func, ExtractedElementR));
       _movss(ExtractedElementR, T);
     }
   } else {
     assert(Ty == IceType_v16i8 || Ty == IceType_v16i1);
     // Spill the value to a stack slot and do the extraction in memory.
     //
     // TODO(wala): use legalize(SourceVectNotLegalized, Legal_Mem) when
     // support for legalizing to mem is implemented.
-    Variable *Slot = Func->template makeVariable(Ty);
+    Variable *Slot = Func-> makeVariable(Ty);
     Slot->setWeight(RegWeight::Zero);
     _movp(Slot, legalizeToVar(SourceVectNotLegalized));
 
     // Compute the location of the element in memory.
     unsigned Offset = Index * typeWidthInBytes(InVectorElementTy);
     typename Traits::X86OperandMem *Loc =
         getMemoryOperandForStackSlot(InVectorElementTy, Slot, Offset);
     _mov(ExtractedElementR, Loc);
   }
 
@@ skipping 144 matching lines @@
       case IceType_v4i1:
         NewTy = IceType_v4i32;
         break;
       case IceType_v8i1:
         NewTy = IceType_v8i16;
         break;
       case IceType_v16i1:
         NewTy = IceType_v16i8;
         break;
       }
-      Variable *NewSrc0 = Func->template makeVariable(NewTy);
-      Variable *NewSrc1 = Func->template makeVariable(NewTy);
+      Variable *NewSrc0 = Func-> makeVariable(NewTy);
+      Variable *NewSrc1 = Func-> makeVariable(NewTy);
       lowerCast(InstCast::create(Func, InstCast::Sext, NewSrc0, Src0));
       lowerCast(InstCast::create(Func, InstCast::Sext, NewSrc1, Src1));
       Src0 = NewSrc0;
       Src1 = NewSrc1;
       Ty = NewTy;
     }
 
     InstIcmp::ICond Condition = Inst->getCondition();
 
     Operand *Src0RM = legalize(Src0, Legal_Reg | Legal_Mem);
@@ skipping 121 matching lines @@
   unsigned Index = ElementIndex->getValue();
   assert(Index < typeNumElements(SourceVectNotLegalized->getType()));
 
   Type Ty = SourceVectNotLegalized->getType();
   Type ElementTy = typeElementType(Ty);
   Type InVectorElementTy = Traits::getInVectorElementType(Ty);
 
   if (ElementTy == IceType_i1) {
     // Expand the element to the appropriate size for it to be inserted
     // in the vector.
-    Variable *Expanded = Func->template makeVariable(InVectorElementTy);
+    Variable *Expanded = Func-> makeVariable(InVectorElementTy);
     InstCast *Cast = InstCast::create(Func, InstCast::Zext, Expanded,
                                       ElementToInsertNotLegalized);
     lowerCast(Cast);
     ElementToInsertNotLegalized = Expanded;
   }
 
   if (Ty == IceType_v8i16 || Ty == IceType_v8i1 ||
       InstructionSet >= Traits::SSE4_1) {
     // Use insertps, pinsrb, pinsrw, or pinsrd.
     Operand *ElementRM =
@@ skipping 70 matching lines @@
       _shufps(T, ElementR, Mask2Constant);
       _movp(Inst->getDest(), T);
     }
   } else {
     assert(Ty == IceType_v16i8 || Ty == IceType_v16i1);
     // Spill the value to a stack slot and perform the insertion in
     // memory.
     //
     // TODO(wala): use legalize(SourceVectNotLegalized, Legal_Mem) when
     // support for legalizing to mem is implemented.
-    Variable *Slot = Func->template makeVariable(Ty);
+    Variable *Slot = Func-> makeVariable(Ty);
     Slot->setWeight(RegWeight::Zero);
     _movp(Slot, legalizeToVar(SourceVectNotLegalized));
 
     // Compute the location of the position to insert in memory.
     unsigned Offset = Index * typeWidthInBytes(InVectorElementTy);
     typename Traits::X86OperandMem *Loc =
         getMemoryOperandForStackSlot(InVectorElementTy, Slot, Offset);
     _store(legalizeToVar(ElementToInsertNotLegalized), Loc);
 
     Variable *T = makeReg(Ty);
@@ skipping 272 matching lines @@
     Call->addArg(Instr->getArg(2));
     lowerCall(Call);
     return;
   }
   case Intrinsics::Memset: {
     // The value operand needs to be extended to a stack slot size
     // because the PNaCl ABI requires arguments to be at least 32 bits
     // wide.
     Operand *ValOp = Instr->getArg(1);
     assert(ValOp->getType() == IceType_i8);
-    Variable *ValExt = Func->template makeVariable(stackSlotType());
+    Variable *ValExt = Func->makeVariable(stackSlotType());
     lowerCast(InstCast::create(Func, InstCast::Zext, ValExt, ValOp));
     InstCall *Call = makeHelperCall(H_call_memset, nullptr, 3);
     Call->addArg(Instr->getArg(0));
     Call->addArg(ValExt);
     Call->addArg(Instr->getArg(2));
     lowerCall(Call);
     return;
   }
   case Intrinsics::NaClReadTP: {
     if (Ctx->getFlags().getUseSandboxing()) {
-      Constant *Zero = Ctx->getConstantZero(IceType_i32);
-      Operand *Src = Traits::X86OperandMem::create(
-          Func, IceType_i32, nullptr, Zero, nullptr, 0,
-          Traits::X86OperandMem::SegReg_GS);
+      Operand *Src = dispatchToConcrete(&Machine::createNaClReadTPSrcOperand);

[John, 2015/07/08 16:37:40]

And here is the "proof of concept" for using dispatchToConcrete. As we move
along in implementing X86 targets this template class will be permeated with
uses of this method (particularly for target-specific lowerings.)

       Variable *Dest = Instr->getDest();
       Variable *T = nullptr;
       _mov(T, Src);
       _mov(Dest, T);
     } else {
       InstCall *Call = makeHelperCall(H_call_read_tp, Instr->getDest(), 0);
       lowerCall(Call);
     }
     return;
   }
@@ skipping 412 matching lines @@
   } else {
     _bsr(T_Dest2, SecondVar);
     _xor(T_Dest2, ThirtyOne);
   }
   _test(SecondVar, SecondVar);
   _cmov(T_Dest2, T_Dest, Traits::Cond::Br_e);
   _mov(DestLo, T_Dest2);
   _mov(DestHi, Ctx->getConstantZero(IceType_i32));
 }
 
-bool isAdd(const Inst *Inst) {
+inline bool isAdd(const Inst *Inst) {
   if (const InstArithmetic *Arith =
           llvm::dyn_cast_or_null<const InstArithmetic>(Inst)) {
     return (Arith->getOp() == InstArithmetic::Add);
   }
   return false;
 }
 
-void dumpAddressOpt(const Cfg *Func, const Variable *Base,
-                    const Variable *Index, uint16_t Shift, int32_t Offset,
-                    const Inst *Reason) {
+inline void dumpAddressOpt(const Cfg *Func, const Variable *Base,
+                           const Variable *Index, uint16_t Shift,
+                           int32_t Offset, const Inst *Reason) {
   if (!BuildDefs::dump())
     return;
   if (!Func->isVerbose(IceV_AddrOpt))
     return;
   OstreamLocker L(Func->getContext());
   Ostream &Str = Func->getContext()->getStrDump();
   Str << "Instruction: ";
   Reason->dumpDecorated(Func);
   Str << "  results in Base=";
   if (Base)
     Base->dump(Func);
   else
     Str << "<null>";
   Str << ", Index=";
   if (Index)
     Index->dump(Func);
   else
     Str << "<null>";
   Str << ", Shift=" << Shift << ", Offset=" << Offset << "\n";
 }
 
-bool matchTransitiveAssign(const VariablesMetadata *VMetadata, Variable *&Var,
-                           const Inst *&Reason) {
+inline bool matchTransitiveAssign(const VariablesMetadata *VMetadata,
+                                  Variable *&Var, const Inst *&Reason) {
   // Var originates from Var=SrcVar ==>
   //   set Var:=SrcVar
   if (Var == nullptr)
     return false;
   if (const Inst *VarAssign = VMetadata->getSingleDefinition(Var)) {
     assert(!VMetadata->isMultiDef(Var));
     if (llvm::isa<InstAssign>(VarAssign)) {
       Operand *SrcOp = VarAssign->getSrc(0);
       assert(SrcOp);
       if (Variable *SrcVar = llvm::dyn_cast<Variable>(SrcOp)) {
         if (!VMetadata->isMultiDef(SrcVar) &&
             // TODO: ensure SrcVar stays single-BB
             true) {
           Var = SrcVar;
           Reason = VarAssign;
           return true;
         }
       }
     }
   }
   return false;
 }
 
-bool matchCombinedBaseIndex(const VariablesMetadata *VMetadata, Variable *&Base,
-                            Variable *&Index, uint16_t &Shift,
-                            const Inst *&Reason) {
+inline bool matchCombinedBaseIndex(const VariablesMetadata *VMetadata,
+                                   Variable *&Base, Variable *&Index,
+                                   uint16_t &Shift, const Inst *&Reason) {
   // Index==nullptr && Base is Base=Var1+Var2 ==>
   //   set Base=Var1, Index=Var2, Shift=0
   if (Base == nullptr)
     return false;
   if (Index != nullptr)
     return false;
   const Inst *BaseInst = VMetadata->getSingleDefinition(Base);
   if (BaseInst == nullptr)
     return false;
   assert(!VMetadata->isMultiDef(Base));
@@ skipping 12 matching lines @@
         Index = Var2;
         Shift = 0; // should already have been 0
         Reason = BaseInst;
         return true;
       }
     }
   }
   return false;
 }
 
-bool matchShiftedIndex(const VariablesMetadata *VMetadata, Variable *&Index,
-                       uint16_t &Shift, const Inst *&Reason) {
+inline bool matchShiftedIndex(const VariablesMetadata *VMetadata,
+                              Variable *&Index, uint16_t &Shift,
+                              const Inst *&Reason) {
   // Index is Index=Var*Const && log2(Const)+Shift<=3 ==>
   //   Index=Var, Shift+=log2(Const)
   if (Index == nullptr)
     return false;
   const Inst *IndexInst = VMetadata->getSingleDefinition(Index);
   if (IndexInst == nullptr)
     return false;
   assert(!VMetadata->isMultiDef(Index));
   if (IndexInst->getSrcSize() < 2)
     return false;
@@ skipping 28 matching lines @@
             Reason = IndexInst;
             return true;
           }
         }
       }
     }
   }
   return false;
 }
 
-bool matchOffsetBase(const VariablesMetadata *VMetadata, Variable *&Base,
-                     int32_t &Offset, const Inst *&Reason) {
+inline bool matchOffsetBase(const VariablesMetadata *VMetadata, Variable *&Base,
+                            int32_t &Offset, const Inst *&Reason) {
   // Base is Base=Var+Const || Base is Base=Const+Var ==>
   //   set Base=Var, Offset+=Const
   // Base is Base=Var-Const ==>
   //   set Base=Var, Offset-=Const
   if (Base == nullptr)
     return false;
   const Inst *BaseInst = VMetadata->getSingleDefinition(Base);
   if (BaseInst == nullptr)
     return false;
   assert(!VMetadata->isMultiDef(Base));
@@ skipping 19 matching lines @@
     if (Utils::WouldOverflowAdd(Offset, MoreOffset))
       return false;
     Base = Var;
     Offset += MoreOffset;
     Reason = BaseInst;
     return true;
   }
   return false;
 }
 
-void computeAddressOpt(Cfg *Func, const Inst *Instr, Variable *&Base,
-                       Variable *&Index, uint16_t &Shift, int32_t &Offset) {
+inline void computeAddressOpt(Cfg *Func, const Inst *Instr, Variable *&Base,
+                              Variable *&Index, uint16_t &Shift,
+                              int32_t &Offset) {
   Func->resetCurrentNode();
   if (Func->isVerbose(IceV_AddrOpt)) {
     OstreamLocker L(Func->getContext());
     Ostream &Str = Func->getContext()->getStrDump();
     Str << "\nStarting computeAddressOpt for instruction:\n  ";
     Instr->dumpDecorated(Func);
   }
   (void)Offset; // TODO: pattern-match for non-zero offsets.
   if (Base == nullptr)
     return;
@@ skipping 168 matching lines @@
     }
     // Lower select without Traits::SSE4.1:
     // a=d?b:c ==>
     //   if elementtype(d) != i1:
     //      d=sext(d);
     //   a=(b&d)|(c&~d);
     Variable *T2 = makeReg(SrcTy);
     // Sign extend the condition operand if applicable.
     if (SrcTy == IceType_v4f32) {
       // The sext operation takes only integer arguments.
-      Variable *T3 = Func->template makeVariable(IceType_v4i32);
+      Variable *T3 = Func-> makeVariable(IceType_v4i32);
       lowerCast(InstCast::create(Func, InstCast::Sext, T3, Condition));
       _movp(T, T3);
     } else if (typeElementType(SrcTy) != IceType_i1) {
       lowerCast(InstCast::create(Func, InstCast::Sext, T, Condition));
     } else {
       Operand *ConditionRM = legalize(Condition, Legal_Reg | Legal_Mem);
       _movp(T, ConditionRM);
     }
     _movp(T2, T);
     _pand(T, SrcTRM);
@@ skipping 184 matching lines @@
   assert(isVectorType(Dest->getType()));
   Type Ty = Dest->getType();
   Type ElementTy = typeElementType(Ty);
   SizeT NumElements = typeNumElements(Ty);
 
   Operand *T = Ctx->getConstantUndef(Ty);
   for (SizeT I = 0; I < NumElements; ++I) {
     Constant *Index = Ctx->getConstantInt32(I);
 
     // Extract the next two inputs.
-    Variable *Op0 = Func->template makeVariable(ElementTy);
+    Variable *Op0 = Func-> makeVariable(ElementTy);
     lowerExtractElement(InstExtractElement::create(Func, Op0, Src0, Index));
-    Variable *Op1 = Func->template makeVariable(ElementTy);
+    Variable *Op1 = Func-> makeVariable(ElementTy);
     lowerExtractElement(InstExtractElement::create(Func, Op1, Src1, Index));
 
     // Perform the arithmetic as a scalar operation.
-    Variable *Res = Func->template makeVariable(ElementTy);
+    Variable *Res = Func-> makeVariable(ElementTy);
     lowerArithmetic(InstArithmetic::create(Func, Kind, Res, Op0, Op1));
 
     // Insert the result into position.
-    Variable *DestT = Func->template makeVariable(Ty);
+    Variable *DestT = Func-> makeVariable(Ty);
     lowerInsertElement(InstInsertElement::create(Func, DestT, T, Res, Index));
     T = DestT;
   }
 
   lowerAssign(InstAssign::create(Func, Dest, T));
 }
 
 /// The following pattern occurs often in lowered C and C++ code:
 ///
 ///   %cmp     = fcmp/icmp pred <n x ty> %src0, %src1
@@ skipping 139 matching lines @@
         PhiLo->addArgument(loOperand(Src), Label);
         PhiHi->addArgument(hiOperand(Src), Label);
       }
       Node->getPhis().push_back(PhiLo);
       Node->getPhis().push_back(PhiHi);
       Phi->setDeleted();
     }
   }
 }
 
-bool isMemoryOperand(const Operand *Opnd) {
+inline bool isMemoryOperand(const Operand *Opnd) {
   if (const auto Var = llvm::dyn_cast<Variable>(Opnd))
     return !Var->hasReg();
   // We treat vector undef values the same as a memory operand,
   // because they do in fact need a register to materialize the vector
   // of zeroes into.
   if (llvm::isa<ConstantUndef>(Opnd))
     return isScalarFloatingType(Opnd->getType()) ||
            isVectorType(Opnd->getType());
   if (llvm::isa<Constant>(Opnd))
     return isScalarFloatingType(Opnd->getType());
@@ skipping 92 matching lines @@
       Variable *Preg = nullptr;
       // TODO(stichnot): Opportunity for register randomization.
       int32_t RegNum = AvailRegsForType.find_first();
       bool IsVector = isVectorType(Dest->getType());
       bool NeedSpill = (RegNum == -1);
       if (NeedSpill) {
         // Pick some register to spill and update RegNum.
         // TODO(stichnot): Opportunity for register randomization.
         RegNum = RegsForType.find_first();
         Preg = getPhysicalRegister(RegNum, Dest->getType());
-        SpillLoc = Func->template makeVariable(Dest->getType());
+        SpillLoc = Func-> makeVariable(Dest->getType());
         // Create a fake def of the physical register to avoid
         // liveness inconsistency problems during late-stage liveness
         // analysis (e.g. asm-verbose mode).
         Context.insert(InstFakeDef::create(Func, Preg));
         if (IsVector)
           _movp(SpillLoc, Preg);
         else
           _mov(SpillLoc, Preg);
       }
       assert(RegNum >= 0);
@@ skipping 309 matching lines @@
   // Do legalization, which contains randomization/pooling
   // or do randomization/pooling.
   return llvm::cast<typename Traits::X86OperandMem>(
       DoLegalize ? legalize(Mem) : randomizeOrPoolImmediate(Mem));
 }
 
 template <class Machine>
 Variable *TargetX86Base<Machine>::makeReg(Type Type, int32_t RegNum) {
   // There aren't any 64-bit integer registers for x86-32.
   assert(Type != IceType_i64);
-  Variable *Reg = Func->template makeVariable(Type);
+  Variable *Reg = Func-> makeVariable(Type);
   if (RegNum == Variable::NoRegister)
     Reg->setWeightInfinite();
   else
     Reg->setRegNum(RegNum);
   return Reg;
 }
 
 template <class Machine> void TargetX86Base<Machine>::postLower() {
   if (Ctx->getFlags().getOptLevel() == Opt_m1)
     return;
@@ skipping 241 matching lines @@
   }
   // the offset is not eligible for blinding or pooling, return the original
   // mem operand
   return MemOperand;
 }
 
 } // end of namespace X86Internal
 } // end of namespace Ice
 
 #endif // SUBZERO_SRC_ICETARGETLOWERINGX86BASEIMPL_H