libvpx: Pull from upstream

source/libvpx/vp9/common/mips/msa/vp9_macros_msa.h

 /*
  *  Copyright (c) 2015 The WebM project authors. All Rights Reserved.
  *
  *  Use of this source code is governed by a BSD-style license
  *  that can be found in the LICENSE file in the root of the source
  *  tree. An additional intellectual property rights grant can be found
  *  in the file PATENTS.  All contributing project authors may
  *  be found in the AUTHORS file in the root of the source tree.
  */
 
@@ skipping 226 matching lines @@
                  Loads word in 'out2' from (psrc + 2 * stride)
                  Loads word in 'out3' from (psrc + 3 * stride)
 */
 #define LW4(psrc, stride, out0, out1, out2, out3) {  \
   out0 = LW((psrc));                                 \
   out1 = LW((psrc) + stride);                        \
   out2 = LW((psrc) + 2 * stride);                    \
   out3 = LW((psrc) + 3 * stride);                    \
 }
 
+/* Description : Load double words with stride
+   Arguments   : Inputs  - psrc    (source pointer to load from)
+                         - stride
+                 Outputs - out0, out1
+   Details     : Loads double word in 'out0' from (psrc)
+                 Loads double word in 'out1' from (psrc + stride)
+*/
+#define LD2(psrc, stride, out0, out1) {  \
+  out0 = LD((psrc));                     \
+  out1 = LD((psrc) + stride);            \
+}
+#define LD4(psrc, stride, out0, out1, out2, out3) {  \
+  LD2((psrc), stride, out0, out1);                   \
+  LD2((psrc) + 2 * stride, stride, out2, out3);      \
+}
+
 /* Description : Store 4 words with stride
    Arguments   : Inputs  - in0, in1, in2, in3, pdst, stride
    Details     : Stores word from 'in0' to (pdst)
                  Stores word from 'in1' to (pdst + stride)
                  Stores word from 'in2' to (pdst + 2 * stride)
                  Stores word from 'in3' to (pdst + 3 * stride)
 */
 #define SW4(in0, in1, in2, in3, pdst, stride) {  \
   SW(in0, (pdst))                                \
   SW(in1, (pdst) + stride);                      \
@@ skipping 100 matching lines @@
    Arguments   : Inputs  - psrc
                  Outputs - out0, out1, out2, out3
 */
 #define LD4x4_SH(psrc, out0, out1, out2, out3) {         \
   out0 = LD_SH(psrc);                                    \
   out2 = LD_SH(psrc + 8);                                \
   out1 = (v8i16)__msa_ilvl_d((v2i64)out0, (v2i64)out0);  \
   out3 = (v8i16)__msa_ilvl_d((v2i64)out2, (v2i64)out2);  \
 }
 
+/* Description : Load 2 vectors of signed word elements with stride
+   Arguments   : Inputs  - psrc    (source pointer to load from)
+                         - stride
+                 Outputs - out0, out1
+                 Return Type - signed word
+*/
+#define LD_SW2(psrc, stride, out0, out1) {  \
+  out0 = LD_SW((psrc));                     \
+  out1 = LD_SW((psrc) + stride);            \
+}
+
 /* Description : Store vectors of 16 byte elements with stride
    Arguments   : Inputs  - in0, in1, stride
                  Outputs - pdst    (destination pointer to store to)
    Details     : Stores 16 byte elements from 'in0' to (pdst)
                  Stores 16 byte elements from 'in1' to (pdst + stride)
 */
 #define ST_B2(RTYPE, in0, in1, pdst, stride) {  \
   ST_B(RTYPE, in0, (pdst));                     \
   ST_B(RTYPE, in1, (pdst) + stride);            \
 }
@@ skipping 29 matching lines @@
   ST_H2(RTYPE, in2, in3, (pdst) + 2 * stride, stride);    \
 }
 #define ST_SH4(...) ST_H4(v8i16, __VA_ARGS__)
 
 #define ST_H8(RTYPE, in0, in1, in2, in3, in4, in5, in6, in7, pdst, stride) {  \
   ST_H4(RTYPE, in0, in1, in2, in3, (pdst), stride);                           \
   ST_H4(RTYPE, in4, in5, in6, in7, (pdst) + 4 * stride, stride);              \
 }
 #define ST_SH8(...) ST_H8(v8i16, __VA_ARGS__)
 
+/* Description : Store vectors of word elements with stride
+   Arguments   : Inputs  - in0, in1, stride
+                         - pdst    (destination pointer to store to)
+   Details     : Store 4 word elements from 'in0' to (pdst)
+                 Store 4 word elements from 'in1' to (pdst + stride)
+*/
+#define ST_SW2(in0, in1, pdst, stride) {  \
+  ST_SW(in0, (pdst));                     \
+  ST_SW(in1, (pdst) + stride);            \
+}
+
 /* Description : Store as 2x4 byte block to destination memory from input vector
    Arguments   : Inputs  - in, stidx, pdst, stride
                  Return Type - unsigned byte
    Details     : Index stidx halfword element from 'in' vector is copied and
                  stored on first line
                  Index stidx+1 halfword element from 'in' vector is copied and
                  stored on second line
                  Index stidx+2 halfword element from 'in' vector is copied and
                  stored on third line
                  Index stidx+3 halfword element from 'in' vector is copied and
                  stored on fourth line
 */
 #define ST2x4_UB(in, stidx, pdst, stride) {         \
   uint16_t out0_m, out1_m, out2_m, out3_m;          \
   uint8_t *pblk_2x4_m = (uint8_t *)(pdst);          \
                                                     \
   out0_m = __msa_copy_u_h((v8i16)in, (stidx));      \
   out1_m = __msa_copy_u_h((v8i16)in, (stidx + 1));  \
   out2_m = __msa_copy_u_h((v8i16)in, (stidx + 2));  \
   out3_m = __msa_copy_u_h((v8i16)in, (stidx + 3));  \
                                                     \
   SH(out0_m, pblk_2x4_m);                           \
   SH(out1_m, pblk_2x4_m + stride);                  \
   SH(out2_m, pblk_2x4_m + 2 * stride);              \
   SH(out3_m, pblk_2x4_m + 3 * stride);              \
 }
 
+/* Description : Store 4x2 byte block to destination memory from input vector
+   Arguments   : Inputs  - in, pdst, stride
+   Details     : Index 0 word element from 'in' vector is copied to a GP
+                 register and stored to (pdst)
+                 Index 1 word element from 'in' vector is copied to a GP
+                 register and stored to (pdst + stride)
+*/
+#define ST4x2_UB(in, pdst, stride) {        \
+  uint32_t out0_m, out1_m;                  \
+  uint8_t *pblk_4x2_m = (uint8_t *)(pdst);  \
+                                            \
+  out0_m = __msa_copy_u_w((v4i32)in, 0);    \
+  out1_m = __msa_copy_u_w((v4i32)in, 1);    \
+                                            \
+  SW(out0_m, pblk_4x2_m);                   \
+  SW(out1_m, pblk_4x2_m + stride);          \
+}
+
 /* Description : Store as 4x4 byte block to destination memory from input vector
    Arguments   : Inputs  - in0, in1, pdst, stride
                  Return Type - unsigned byte
    Details     : Idx0 word element from input vector 'in0' is copied and stored
                  on first line
                  Idx1 word element from input vector 'in0' is copied and stored
                  on second line
                  Idx2 word element from input vector 'in1' is copied and stored
                  on third line
                  Idx3 word element from input vector 'in1' is copied and stored
@@ skipping 22 matching lines @@
    Details     : Index 0 double word element from input vector 'in' is copied
                  and stored to destination memory at (pdst)
 */
 #define ST8x1_UB(in, pdst) {              \
   uint64_t out0_m;                        \
                                           \
   out0_m = __msa_copy_u_d((v2i64)in, 0);  \
   SD(out0_m, pdst);                       \
 }
 
+/* Description : Store as 8x2 byte block to destination memory from input vector
+   Arguments   : Inputs  - in, pdst, stride
+   Details     : Index 0 double word element from input vector 'in' is copied
+                 and stored to destination memory at (pdst)
+                 Index 1 double word element from input vector 'in' is copied
+                 and stored to destination memory at (pdst + stride)
+*/
+#define ST8x2_UB(in, pdst, stride) {        \
+  uint64_t out0_m, out1_m;                  \
+  uint8_t *pblk_8x2_m = (uint8_t *)(pdst);  \
+                                            \
+  out0_m = __msa_copy_u_d((v2i64)in, 0);    \
+  out1_m = __msa_copy_u_d((v2i64)in, 1);    \
+                                            \
+  SD(out0_m, pblk_8x2_m);                   \
+  SD(out1_m, pblk_8x2_m + stride);          \
+}
+
 /* Description : Store as 8x4 byte block to destination memory from input
                  vectors
    Arguments   : Inputs  - in0, in1, pdst, stride
    Details     : Index 0 double word element from input vector 'in0' is copied
                  and stored to destination memory at (pblk_8x4_m)
                  Index 1 double word element from input vector 'in0' is copied
                  and stored to destination memory at (pblk_8x4_m + stride)
                  Index 0 double word element from input vector 'in1' is copied
                  and stored to destination memory at (pblk_8x4_m + 2 * stride)
                  Index 1 double word element from input vector 'in1' is copied
@@ skipping 173 matching lines @@
 #define DOTP_SH2_SW(...) DOTP_SH2(v4i32, __VA_ARGS__)
 
 #define DOTP_SH4(RTYPE, mult0, mult1, mult2, mult3,         \
                  cnst0, cnst1, cnst2, cnst3,                \
                  out0, out1, out2, out3) {                  \
   DOTP_SH2(RTYPE, mult0, mult1, cnst0, cnst1, out0, out1);  \
   DOTP_SH2(RTYPE, mult2, mult3, cnst2, cnst3, out2, out3);  \
 }
 #define DOTP_SH4_SW(...) DOTP_SH4(v4i32, __VA_ARGS__)
 
+/* Description : Dot product of word vector elements
+   Arguments   : Inputs  - mult0, mult1
+                           cnst0, cnst1
+                 Outputs - out0, out1
+                 Return Type - signed word
+   Details     : Signed word elements from mult0 are multiplied with
+                 signed word elements from cnst0 producing a result
+                 twice the size of input i.e. signed double word.
+                 Then this multiplication results of adjacent odd-even elements
+                 are added together and stored to the out vector
+                 (2 signed double word results)
+*/
+#define DOTP_SW2(RTYPE, mult0, mult1, cnst0, cnst1, out0, out1) {  \
+  out0 = (RTYPE)__msa_dotp_s_d((v4i32)mult0, (v4i32)cnst0);        \
+  out1 = (RTYPE)__msa_dotp_s_d((v4i32)mult1, (v4i32)cnst1);        \
+}
+#define DOTP_SW2_SD(...) DOTP_SW2(v2i64, __VA_ARGS__)
+
 /* Description : Dot product & addition of byte vector elements
    Arguments   : Inputs  - mult0, mult1
                            cnst0, cnst1
                  Outputs - out0, out1
                  Return Type - signed halfword
    Details     : Signed byte elements from mult0 are multiplied with
                  signed byte elements from cnst0 producing a result
                  twice the size of input i.e. signed halfword.
                  Then this multiplication results of adjacent odd-even elements
                  are added to the out vector
                  (2 signed halfword results)
 */
 #define DPADD_SB2(RTYPE, mult0, mult1, cnst0, cnst1, out0, out1) {         \
   out0 = (RTYPE)__msa_dpadd_s_h((v8i16)out0, (v16i8)mult0, (v16i8)cnst0);  \
   out1 = (RTYPE)__msa_dpadd_s_h((v8i16)out1, (v16i8)mult1, (v16i8)cnst1);  \
 }
 #define DPADD_SB2_SH(...) DPADD_SB2(v8i16, __VA_ARGS__)
 
 #define DPADD_SB4(RTYPE, mult0, mult1, mult2, mult3,                     \
                   cnst0, cnst1, cnst2, cnst3, out0, out1, out2, out3) {  \
   DPADD_SB2(RTYPE, mult0, mult1, cnst0, cnst1, out0, out1);              \
   DPADD_SB2(RTYPE, mult2, mult3, cnst2, cnst3, out2, out3);              \
 }
 #define DPADD_SB4_SH(...) DPADD_SB4(v8i16, __VA_ARGS__)
 
+/* Description : Dot product & addition of halfword vector elements
+   Arguments   : Inputs  - mult0, mult1
+                           cnst0, cnst1
+                 Outputs - out0, out1
+                 Return Type - as per RTYPE
+   Details     : Signed halfword elements from 'mult0' are multiplied with
+                 signed halfword elements from 'cnst0' producing a result
+                 twice the size of input i.e. signed word.
+                 The multiplication result of adjacent odd-even elements
+                 are added to the 'out0' vector
+*/
+#define DPADD_SH2(RTYPE, mult0, mult1, cnst0, cnst1, out0, out1) {         \
+  out0 = (RTYPE)__msa_dpadd_s_w((v4i32)out0, (v8i16)mult0, (v8i16)cnst0);  \
+  out1 = (RTYPE)__msa_dpadd_s_w((v4i32)out1, (v8i16)mult1, (v8i16)cnst1);  \
+}
+#define DPADD_SH2_SW(...) DPADD_SH2(v4i32, __VA_ARGS__)
+
+/* Description : Dot product & addition of double word vector elements
+   Arguments   : Inputs  - mult0, mult1
+                 Outputs - out0, out1
+                 Return Type - as per RTYPE
+   Details     : Each signed word element from 'mult0' is multiplied with itself
+                 producing an intermediate result twice the size of input
+                 i.e. signed double word
+                 The multiplication result of adjacent odd-even elements
+                 are added to the 'out0' vector
+*/
+#define DPADD_SD2(RTYPE, mult0, mult1, out0, out1) {                       \
+  out0 = (RTYPE)__msa_dpadd_s_d((v2i64)out0, (v4i32)mult0, (v4i32)mult0);  \
+  out1 = (RTYPE)__msa_dpadd_s_d((v2i64)out1, (v4i32)mult1, (v4i32)mult1);  \
+}
+#define DPADD_SD2_SD(...) DPADD_SD2(v2i64, __VA_ARGS__)
+
 /* Description : Minimum values between unsigned elements of
                  either vector are copied to the output vector
    Arguments   : Inputs  - in0, in1, min_vec
                  Outputs - in0, in1, (in place)
                  Return Type - unsigned halfword
    Details     : Minimum of unsigned halfword element values from 'in0' and
                  'min_value' are written to output vector 'in0'
 */
 #define MIN_UH2(RTYPE, in0, in1, min_vec) {         \
   in0 = (RTYPE)__msa_min_u_h((v8u16)in0, min_vec);  \
@@ skipping 23 matching lines @@
 })
 #define CLIP_SH2_0_255(in0, in1) {  \
   in0 = CLIP_SH_0_255(in0);         \
   in1 = CLIP_SH_0_255(in1);         \
 }
 #define CLIP_SH4_0_255(in0, in1, in2, in3) {  \
   CLIP_SH2_0_255(in0, in1);                   \
   CLIP_SH2_0_255(in2, in3);                   \
 }
 
+/* Description : Addition of 4 signed word elements
+                 4 signed word elements of input vector are added together and
+                 the resulting integer sum is returned
+   Arguments   : Inputs  - in       (signed word vector)
+                 Outputs - sum_m    (i32 sum)
+                 Return Type - signed word
+*/
+#define HADD_SW_S32(in) ({                        \
+  v2i64 res0_m, res1_m;                           \
+  int32_t sum_m;                                  \
+                                                  \
+  res0_m = __msa_hadd_s_d((v4i32)in, (v4i32)in);  \
+  res1_m = __msa_splati_d(res0_m, 1);             \
+  res0_m = res0_m + res1_m;                       \
+  sum_m = __msa_copy_s_w((v4i32)res0_m, 0);       \
+  sum_m;                                          \
+})
+
+/* Description : Horizontal addition of unsigned byte vector elements
+   Arguments   : Inputs  - in0, in1
+                 Outputs - out0, out1
+                 Return Type - as per RTYPE
+   Details     : Each unsigned odd byte element from 'in0' is added to
+                 even unsigned byte element from 'in0' (pairwise) and the
+                 halfword result is stored in 'out0'
+*/
+#define HADD_UB2(RTYPE, in0, in1, out0, out1) {          \
+  out0 = (RTYPE)__msa_hadd_u_h((v16u8)in0, (v16u8)in0);  \
+  out1 = (RTYPE)__msa_hadd_u_h((v16u8)in1, (v16u8)in1);  \
+}
+#define HADD_UB2_UH(...) HADD_UB2(v8u16, __VA_ARGS__)
+
+#define HADD_UB4(RTYPE, in0, in1, in2, in3, out0, out1, out2, out3) {  \
+  HADD_UB2(RTYPE, in0, in1, out0, out1);                               \
+  HADD_UB2(RTYPE, in2, in3, out2, out3);                               \
+}
+#define HADD_UB4_UH(...) HADD_UB4(v8u16, __VA_ARGS__)
+
+/* Description : Horizontal subtraction of unsigned byte vector elements
+   Arguments   : Inputs  - in0, in1
+                 Outputs - out0, out1
+                 Return Type - as per RTYPE
+   Details     : Each unsigned odd byte element from 'in0' is subtracted from
+                 even unsigned byte element from 'in0' (pairwise) and the
+                 halfword result is written to 'out0'
+*/
+#define HSUB_UB2(RTYPE, in0, in1, out0, out1) {          \
+  out0 = (RTYPE)__msa_hsub_u_h((v16u8)in0, (v16u8)in0);  \
+  out1 = (RTYPE)__msa_hsub_u_h((v16u8)in1, (v16u8)in1);  \
+}
+#define HSUB_UB2_SH(...) HSUB_UB2(v8i16, __VA_ARGS__)
+
+/* Description : Horizontal subtraction of signed halfword vector elements
+   Arguments   : Inputs  - in0, in1
+                 Outputs - out0, out1
+                 Return Type - as per RTYPE
+   Details     : Each signed odd halfword element from 'in0' is subtracted from
+                 even signed halfword element from 'in0' (pairwise) and the
+                 word result is written to 'out0'
+*/
+#define HSUB_UH2(RTYPE, in0, in1, out0, out1) {          \
+  out0 = (RTYPE)__msa_hsub_s_w((v8i16)in0, (v8i16)in0);  \
+  out1 = (RTYPE)__msa_hsub_s_w((v8i16)in1, (v8i16)in1);  \
+}
+#define HSUB_UH2_SW(...) HSUB_UH2(v4i32, __VA_ARGS__)
+
 /* Description : Insert specified word elements from input vectors to 1
                  destination vector
    Arguments   : Inputs  - in0, in1, in2, in3 (4 input vectors)
                  Outputs - out                (output vector)
                  Return Type - as per RTYPE
 */
 #define INSERT_W2(RTYPE, in0, in1, out) {           \
   out = (RTYPE)__msa_insert_w((v4i32)out, 0, in0);  \
   out = (RTYPE)__msa_insert_w((v4i32)out, 1, in1);  \
 }
 #define INSERT_W2_SB(...) INSERT_W2(v16i8, __VA_ARGS__)
 
+#define INSERT_W4(RTYPE, in0, in1, in2, in3, out) {  \
+  out = (RTYPE)__msa_insert_w((v4i32)out, 0, in0);   \
+  out = (RTYPE)__msa_insert_w((v4i32)out, 1, in1);   \
+  out = (RTYPE)__msa_insert_w((v4i32)out, 2, in2);   \
+  out = (RTYPE)__msa_insert_w((v4i32)out, 3, in3);   \
+}
+#define INSERT_W4_UB(...) INSERT_W4(v16u8, __VA_ARGS__)
+#define INSERT_W4_SB(...) INSERT_W4(v16i8, __VA_ARGS__)
+
+/* Description : Insert specified double word elements from input vectors to 1
+                 destination vector
+   Arguments   : Inputs  - in0, in1      (2 input vectors)
+                 Outputs - out           (output vector)
+                 Return Type - as per RTYPE
+*/
+#define INSERT_D2(RTYPE, in0, in1, out) {           \
+  out = (RTYPE)__msa_insert_d((v2i64)out, 0, in0);  \
+  out = (RTYPE)__msa_insert_d((v2i64)out, 1, in1);  \
+}
+#define INSERT_D2_UB(...) INSERT_D2(v16u8, __VA_ARGS__)
+#define INSERT_D2_SB(...) INSERT_D2(v16i8, __VA_ARGS__)
+
 /* Description : Interleave even byte elements from vectors
    Arguments   : Inputs  - in0, in1, in2, in3
                  Outputs - out0, out1
                  Return Type - as per RTYPE
    Details     : Even byte elements of 'in0' and even byte
                  elements of 'in1' are interleaved and copied to 'out0'
                  Even byte elements of 'in2' and even byte
                  elements of 'in3' are interleaved and copied to 'out1'
 */
 #define ILVEV_B2(RTYPE, in0, in1, in2, in3, out0, out1) {  \
@@ skipping 13 matching lines @@
                  elements of 'in3' are interleaved and copied to 'out1'
 */
 #define ILVEV_H2(RTYPE, in0, in1, in2, in3, out0, out1) {  \
   out0 = (RTYPE)__msa_ilvev_h((v8i16)in1, (v8i16)in0);     \
   out1 = (RTYPE)__msa_ilvev_h((v8i16)in3, (v8i16)in2);     \
 }
 #define ILVEV_H2_UB(...) ILVEV_H2(v16u8, __VA_ARGS__)
 #define ILVEV_H2_SH(...) ILVEV_H2(v8i16, __VA_ARGS__)
 #define ILVEV_H2_SW(...) ILVEV_H2(v4i32, __VA_ARGS__)
 
+/* Description : Interleave even word elements from vectors
+   Arguments   : Inputs  - in0, in1, in2, in3
+                 Outputs - out0, out1
+                 Return Type - as per RTYPE
+   Details     : Even word elements of 'in0' and 'in1' are interleaved
+                 and written to 'out0'
+*/
+#define ILVEV_W2(RTYPE, in0, in1, in2, in3, out0, out1) {  \
+  out0 = (RTYPE)__msa_ilvev_w((v4i32)in1, (v4i32)in0);     \
+  out1 = (RTYPE)__msa_ilvev_w((v4i32)in3, (v4i32)in2);     \
+}
+#define ILVEV_W2_SB(...) ILVEV_W2(v16i8, __VA_ARGS__)
+
 /* Description : Interleave even double word elements from vectors
    Arguments   : Inputs  - in0, in1, in2, in3
                  Outputs - out0, out1
                  Return Type - as per RTYPE
    Details     : Even double word elements of 'in0' and even double word
                  elements of 'in1' are interleaved and copied to 'out0'
                  Even double word elements of 'in2' and even double word
                  elements of 'in3' are interleaved and copied to 'out1'
 */
 #define ILVEV_D2(RTYPE, in0, in1, in2, in3, out0, out1) {  \
@@ skipping 198 matching lines @@
 #define ILVRL_W2_SH(...) ILVRL_W2(v8i16, __VA_ARGS__)
 #define ILVRL_W2_SW(...) ILVRL_W2(v4i32, __VA_ARGS__)
 
 /* Description : Saturate the halfword element values to the max
                  unsigned value of (sat_val+1 bits)
                  The element data width remains unchanged
    Arguments   : Inputs  - in0, in1, in2, in3, sat_val
                  Outputs - in0, in1, in2, in3 (in place)
                  Return Type - unsigned halfword
    Details     : Each unsigned halfword element from 'in0' is saturated to the
-                 value generated with (sat_val+1) bit range
-                 Results are in placed to original vectors
+                 value generated with (sat_val+1) bit range.
+                 The results are stored in place
 */
 #define SAT_UH2(RTYPE, in0, in1, sat_val) {         \
   in0 = (RTYPE)__msa_sat_u_h((v8u16)in0, sat_val);  \
   in1 = (RTYPE)__msa_sat_u_h((v8u16)in1, sat_val);  \
 }
 #define SAT_UH2_UH(...) SAT_UH2(v8u16, __VA_ARGS__)
 
 #define SAT_UH4(RTYPE, in0, in1, in2, in3, sat_val) {  \
   SAT_UH2(RTYPE, in0, in1, sat_val);                   \
   SAT_UH2(RTYPE, in2, in3, sat_val)                    \
 }
 #define SAT_UH4_UH(...) SAT_UH4(v8u16, __VA_ARGS__)
 
 /* Description : Saturate the halfword element values to the max
                  unsigned value of (sat_val+1 bits)
                  The element data width remains unchanged
    Arguments   : Inputs  - in0, in1, in2, in3, sat_val
                  Outputs - in0, in1, in2, in3 (in place)
                  Return Type - unsigned halfword
    Details     : Each unsigned halfword element from 'in0' is saturated to the
                  value generated with (sat_val+1) bit range
-                 Results are in placed to original vectors
+                 The results are stored in place
 */
 #define SAT_SH2(RTYPE, in0, in1, sat_val) {         \
   in0 = (RTYPE)__msa_sat_s_h((v8i16)in0, sat_val);  \
   in1 = (RTYPE)__msa_sat_s_h((v8i16)in1, sat_val);  \
 }
 #define SAT_SH2_SH(...) SAT_SH2(v8i16, __VA_ARGS__)
 
 #define SAT_SH4(RTYPE, in0, in1, in2, in3, sat_val) {  \
   SAT_SH2(RTYPE, in0, in1, sat_val);                   \
   SAT_SH2(RTYPE, in2, in3, sat_val);                   \
@@ skipping 99 matching lines @@
   PCKEV_D2(RTYPE, in0, in1, in2, in3, out0, out1);               \
   PCKEV_D2(RTYPE, in4, in5, in6, in7, out2, out3);               \
 }
 #define PCKEV_D4_UB(...) PCKEV_D4(v16u8, __VA_ARGS__)
 
 /* Description : Each byte element is logically xor'ed with immediate 128
    Arguments   : Inputs  - in0, in1
                  Outputs - in0, in1 (in-place)
                  Return Type - as per RTYPE
    Details     : Each unsigned byte element from input vector 'in0' is
-                 logically xor'ed with 128 and result is in-place stored in
+                 logically xor'ed with 128 and the result is in-place stored in
                  'in0' vector
                  Each unsigned byte element from input vector 'in1' is
-                 logically xor'ed with 128 and result is in-place stored in
+                 logically xor'ed with 128 and the result is in-place stored in
                  'in1' vector
                  Similar for other pairs
 */
 #define XORI_B2_128(RTYPE, in0, in1) {         \
   in0 = (RTYPE)__msa_xori_b((v16u8)in0, 128);  \
   in1 = (RTYPE)__msa_xori_b((v16u8)in1, 128);  \
 }
 #define XORI_B2_128_UB(...) XORI_B2_128(v16u8, __VA_ARGS__)
 #define XORI_B2_128_SB(...) XORI_B2_128(v16i8, __VA_ARGS__)
 
 #define XORI_B3_128(RTYPE, in0, in1, in2) {    \
   XORI_B2_128(RTYPE, in0, in1);                \
   in2 = (RTYPE)__msa_xori_b((v16u8)in2, 128);  \
 }
 #define XORI_B3_128_SB(...) XORI_B3_128(v16i8, __VA_ARGS__)
 
 #define XORI_B4_128(RTYPE, in0, in1, in2, in3) {  \
   XORI_B2_128(RTYPE, in0, in1);                   \
   XORI_B2_128(RTYPE, in2, in3);                   \
 }
 #define XORI_B4_128_UB(...) XORI_B4_128(v16u8, __VA_ARGS__)
 #define XORI_B4_128_SB(...) XORI_B4_128(v16i8, __VA_ARGS__)
 
 #define XORI_B7_128(RTYPE, in0, in1, in2, in3, in4, in5, in6) {  \
   XORI_B4_128(RTYPE, in0, in1, in2, in3);                        \
   XORI_B3_128(RTYPE, in4, in5, in6);                             \
 }
 #define XORI_B7_128_SB(...) XORI_B7_128(v16i8, __VA_ARGS__)
 
+/* Description : Average of signed halfword elements -> (a + b) / 2
+   Arguments   : Inputs  - in0, in1, in2, in3, in4, in5, in6, in7
+                 Outputs - out0, out1, out2, out3
+                 Return Type - as per RTYPE
+   Details     : Each signed halfword element from 'in0' is added to each
+                 signed halfword element of 'in1' with full precision resulting
+                 in one extra bit in the result. The result is then divided by
+                 2 and written to 'out0'
+*/
+#define AVE_SH4(RTYPE, in0, in1, in2, in3, in4, in5, in6, in7,  \
+                out0, out1, out2, out3) {                       \
+  out0 = (RTYPE)__msa_ave_s_h((v8i16)in0, (v8i16)in1);          \
+  out1 = (RTYPE)__msa_ave_s_h((v8i16)in2, (v8i16)in3);          \
+  out2 = (RTYPE)__msa_ave_s_h((v8i16)in4, (v8i16)in5);          \
+  out3 = (RTYPE)__msa_ave_s_h((v8i16)in6, (v8i16)in7);          \
+}
+#define AVE_SH4_SH(...) AVE_SH4(v8i16, __VA_ARGS__)
+
 /* Description : Addition of signed halfword elements and signed saturation
    Arguments   : Inputs  - in0, in1, in2, in3
                  Outputs - out0, out1
                  Return Type - as per RTYPE
    Details     : Signed halfword elements from 'in0' are added to signed
                  halfword elements of 'in1'. The result is then signed saturated
                  between -32768 to +32767 (as per halfword data type)
                  Similar for other pairs
 */
 #define ADDS_SH2(RTYPE, in0, in1, in2, in3, out0, out1) {  \
   out0 = (RTYPE)__msa_adds_s_h((v8i16)in0, (v8i16)in1);    \
   out1 = (RTYPE)__msa_adds_s_h((v8i16)in2, (v8i16)in3);    \
 }
 #define ADDS_SH2_SH(...) ADDS_SH2(v8i16, __VA_ARGS__)
 
 #define ADDS_SH4(RTYPE, in0, in1, in2, in3, in4, in5, in6, in7,  \
                  out0, out1, out2, out3) {                       \
   ADDS_SH2(RTYPE, in0, in1, in2, in3, out0, out1);               \
   ADDS_SH2(RTYPE, in4, in5, in6, in7, out2, out3);               \
 }
 #define ADDS_SH4_SH(...) ADDS_SH4(v8i16, __VA_ARGS__)
 
+/* Description : Shift left all elements of vector (generic for all data types)
+   Arguments   : Inputs  - in0, in1, in2, in3, shift
+                 Outputs - in0, in1, in2, in3 (in place)
+                 Return Type - as per input vector RTYPE
+   Details     : Each element of vector 'in0' is left shifted by 'shift' and
+                 the result is in place written to 'in0'
+                 Similar for other pairs
+*/
+#define SLLI_4V(in0, in1, in2, in3, shift) {  \
+  in0 = in0 << shift;                         \
+  in1 = in1 << shift;                         \
+  in2 = in2 << shift;                         \
+  in3 = in3 << shift;                         \
+}
+
 /* Description : Arithmetic shift right all elements of vector
                  (generic for all data types)
    Arguments   : Inputs  - in0, in1, in2, in3, shift
                  Outputs - in0, in1, in2, in3 (in place)
                  Return Type - as per input vector RTYPE
    Details     : Each element of vector 'in0' is right shifted by 'shift' and
-                 result is in place written to 'in0'
+                 the result is in place written to 'in0'
                  Here, 'shift' is GP variable passed in
                  Similar for other pairs
 */
 #define SRA_4V(in0, in1, in2, in3, shift) {  \
   in0 = in0 >> shift;                        \
   in1 = in1 >> shift;                        \
   in2 = in2 >> shift;                        \
   in3 = in3 >> shift;                        \
 }
 
+/* Description : Shift right arithmetic rounded words
+   Arguments   : Inputs  - in0, in1, shift
+                 Outputs - in place operation
+                 Return Type - as per RTYPE
+   Details     : Each element of vector 'in0' is shifted right arithmetically by
+                 the number of bits in the corresponding element in the vector
+                 'shift'. The last discarded bit is added to shifted value for
+                 rounding and the result is written in-place.
+                 'shift' is a vector.
+*/
+#define SRAR_W2(RTYPE, in0, in1, shift) {               \
+  in0 = (RTYPE)__msa_srar_w((v4i32)in0, (v4i32)shift);  \
+  in1 = (RTYPE)__msa_srar_w((v4i32)in1, (v4i32)shift);  \
+}
+
+#define SRAR_W4(RTYPE, in0, in1, in2, in3, shift) {  \
+  SRAR_W2(RTYPE, in0, in1, shift)                    \
+  SRAR_W2(RTYPE, in2, in3, shift)                    \
+}
+#define SRAR_W4_SW(...) SRAR_W4(v4i32, __VA_ARGS__)
+
 /* Description : Shift right arithmetic rounded (immediate)
    Arguments   : Inputs  - in0, in1, in2, in3, shift
                  Outputs - in0, in1, in2, in3 (in place)
                  Return Type - as per RTYPE
    Details     : Each element of vector 'in0' is shifted right arithmetic by
                  value in 'shift'.
                  The last discarded bit is added to shifted value for rounding
                  and the result is in place written to 'in0'
                  Similar for other pairs
 */
@@ skipping 26 matching lines @@
   in1 = (RTYPE)__msa_srari_w((v4i32)in1, shift);  \
 }
 #define SRARI_W2_SW(...) SRARI_W2(v4i32, __VA_ARGS__)
 
 #define SRARI_W4(RTYPE, in0, in1, in2, in3, shift) {  \
   SRARI_W2(RTYPE, in0, in1, shift);                   \
   SRARI_W2(RTYPE, in2, in3, shift);                   \
 }
 #define SRARI_W4_SW(...) SRARI_W4(v4i32, __VA_ARGS__)
 
+/* Description : Logical shift right all elements of vector (immediate)
+   Arguments   : Inputs  - in0, in1, in2, in3, shift
+                 Outputs - out0, out1, out2, out3
+                 Return Type - as per RTYPE
+   Details     : Each element of vector 'in0' is right shifted by 'shift' and
+                 the result is written in-place. 'shift' is an immediate value.
+*/
+#define SRLI_H4(RTYPE, in0, in1, in2, in3, out0, out1, out2, out3, shift) {  \
+  out0 = (RTYPE)__msa_srli_h((v8i16)in0, shift);                             \
+  out1 = (RTYPE)__msa_srli_h((v8i16)in1, shift);                             \
+  out2 = (RTYPE)__msa_srli_h((v8i16)in2, shift);                             \
+  out3 = (RTYPE)__msa_srli_h((v8i16)in3, shift);                             \
+}
+#define SRLI_H4_SH(...) SRLI_H4(v8i16, __VA_ARGS__)
+
+/* Description : Multiplication of pairs of vectors
+   Arguments   : Inputs  - in0, in1, in2, in3
+                 Outputs - out0, out1
+   Details     : Each element from 'in0' is multiplied with elements from 'in1'
+                 and the result is written to 'out0'
+*/
+#define MUL2(in0, in1, in2, in3, out0, out1) {  \
+  out0 = in0 * in1;                             \
+  out1 = in2 * in3;                             \
+}
+#define MUL4(in0, in1, in2, in3, in4, in5, in6, in7,  \
+             out0, out1, out2, out3) {                \
+  MUL2(in0, in1, in2, in3, out0, out1);               \
+  MUL2(in4, in5, in6, in7, out2, out3);               \
+}
+
 /* Description : Addition of 2 pairs of vectors
    Arguments   : Inputs  - in0, in1, in2, in3
                  Outputs - out0, out1
    Details     : Each element from 2 pairs vectors is added and 2 results are
                  produced
 */
 #define ADD2(in0, in1, in2, in3, out0, out1) {  \
   out0 = in0 + in1;                             \
   out1 = in2 + in3;                             \
 }
@@ skipping 42 matching lines @@
                  Return Type - signed halfword
    Details     : Zero extended right half of vector is returned in 'out0'
                  Zero extended left half of vector is returned in 'out1'
 */
 #define UNPCK_UB_SH(in, out0, out1) {   \
   v16i8 zero_m = { 0 };                 \
                                         \
   ILVRL_B2_SH(zero_m, in, out0, out1);  \
 }
 
+/* Description : Sign extend halfword elements from input vector and return
+                 result in pair of vectors
+   Arguments   : Inputs  - in           (1 input halfword vector)
+                 Outputs - out0, out1   (sign extended 2 word vectors)
+                 Return Type - signed word
+   Details     : Sign bit of halfword elements from input vector 'in' is
+                 extracted and interleaved right with same vector 'in0' to
+                 generate 4 signed word elements in 'out0'
+                 Then interleaved left with same vector 'in0' to
+                 generate 4 signed word elements in 'out1'
+*/
+#define UNPCK_SH_SW(in, out0, out1) {    \
+  v8i16 tmp_m;                           \
+                                         \
+  tmp_m = __msa_clti_s_h((v8i16)in, 0);  \
+  ILVRL_H2_SW(tmp_m, in, out0, out1);    \
+}
+
 /* Description : Butterfly of 4 input vectors
    Arguments   : Inputs  - in0, in1, in2, in3
                  Outputs - out0, out1, out2, out3
    Details     : Butterfly operation
 */
 #define BUTTERFLY_4(in0, in1, in2, in3, out0, out1, out2, out3) {  \
   out0 = in0 + in3;                                                \
   out1 = in1 + in2;                                                \
                                                                    \
   out2 = in1 - in2;                                                \
@@ skipping 11 matching lines @@
   out1 = in1 + in6;                                                    \
   out2 = in2 + in5;                                                    \
   out3 = in3 + in4;                                                    \
                                                                        \
   out4 = in3 - in4;                                                    \
   out5 = in2 - in5;                                                    \
   out6 = in1 - in6;                                                    \
   out7 = in0 - in7;                                                    \
 }
 
+/* Description : Butterfly of 16 input vectors
+   Arguments   : Inputs  - in0 ...  in15
+                 Outputs - out0 .. out15
+   Details     : Butterfly operation
+*/
+#define BUTTERFLY_16(in0, in1, in2, in3, in4, in5, in6, in7,                  \
+                     in8, in9,  in10, in11, in12, in13, in14, in15,           \
+                     out0, out1, out2, out3, out4, out5, out6, out7,          \
+                     out8, out9, out10, out11, out12, out13, out14, out15) {  \
+  out0 = in0 + in15;                                                          \
+  out1 = in1 + in14;                                                          \
+  out2 = in2 + in13;                                                          \
+  out3 = in3 + in12;                                                          \
+  out4 = in4 + in11;                                                          \
+  out5 = in5 + in10;                                                          \
+  out6 = in6 + in9;                                                           \
+  out7 = in7 + in8;                                                           \
+                                                                              \
+  out8 = in7 - in8;                                                           \
+  out9 = in6 - in9;                                                           \
+  out10 = in5 - in10;                                                         \
+  out11 = in4 - in11;                                                         \
+  out12 = in3 - in12;                                                         \
+  out13 = in2 - in13;                                                         \
+  out14 = in1 - in14;                                                         \
+  out15 = in0 - in15;                                                         \
+}
+
 /* Description : Transposes input 8x8 byte block
    Arguments   : Inputs  - in0, in1, in2, in3, in4, in5, in6, in7
                            (input 8x8 byte block)
                  Outputs - out0, out1, out2, out3, out4, out5, out6, out7
                            (output 8x8 byte block)
                  Return Type - unsigned byte
    Details     :
 */
 #define TRANSPOSE8x8_UB(RTYPE, in0, in1, in2, in3, in4, in5, in6, in7,     \
                         out0, out1, out2, out3, out4, out5, out6, out7) {  \
@@ skipping 193 matching lines @@
   out2_m = __msa_copy_u_w((v4i32)dst1_m, 0);                    \
   out3_m = __msa_copy_u_w((v4i32)dst1_m, 1);                    \
   SW4(out0_m, out1_m, out2_m, out3_m, pdst, stride);            \
 }
 
 /* Description : Pack even elements of input vectors & xor with 128
    Arguments   : Inputs  - in0, in1
                  Outputs - out_m
                  Return Type - unsigned byte
    Details     : Signed byte even elements from 'in0' and 'in1' are packed
-                 together in one vector and the resulted vector is xor'ed with
+                 together in one vector and the resulting vector is xor'ed with
                  128 to shift the range from signed to unsigned byte
 */
 #define PCKEV_XORI128_UB(in0, in1) ({                    \
   v16u8 out_m;                                           \
                                                          \
   out_m = (v16u8)__msa_pckev_b((v16i8)in1, (v16i8)in0);  \
   out_m = (v16u8)__msa_xori_b((v16u8)out_m, 128);        \
   out_m;                                                 \
 })
 
@@ skipping 33 matching lines @@
   v8u16 tmp1_m;                                                \
                                                                \
   tmp0_m = __msa_vshf_b((v16i8)mask, (v16i8)in1, (v16i8)in0);  \
   tmp1_m = __msa_dotp_u_h((v16u8)tmp0_m, (v16u8)coeff);        \
   tmp1_m = (v8u16)__msa_srari_h((v8i16)tmp1_m, shift);         \
   tmp1_m = __msa_sat_u_h(tmp1_m, shift);                       \
                                                                \
   tmp1_m;                                                      \
 })
 #endif  /* VP9_COMMON_MIPS_MSA_VP9_MACROS_MSA_H_ */