| Index: src/compiler/arm/instruction-selector-arm.cc
|
| diff --git a/src/compiler/arm/instruction-selector-arm.cc b/src/compiler/arm/instruction-selector-arm.cc
|
| index b5324544600c506a69813c309e691a49e3d8bb9d..d9f8f8b1de5bdf92010aaff3c02f4d759909da0a 100644
|
| --- a/src/compiler/arm/instruction-selector-arm.cc
|
| +++ b/src/compiler/arm/instruction-selector-arm.cc
|
| @@ -1166,9 +1166,7 @@ void InstructionSelector::VisitTailCall(Node* node) {
|
| DCHECK_EQ(0, descriptor->flags() & CallDescriptor::kNeedsNopAfterCall);
|
|
|
| // TODO(turbofan): Relax restriction for stack parameters.
|
| - if (descriptor->UsesOnlyRegisters() &&
|
| - descriptor->HasSameReturnLocationsAs(
|
| - linkage()->GetIncomingDescriptor())) {
|
| + if (linkage()->GetIncomingDescriptor()->CanTailCall(node)) {
|
| CallBuffer buffer(zone(), descriptor, nullptr);
|
|
|
| // Compute InstructionOperands for inputs and outputs.
|
| @@ -1177,8 +1175,6 @@ void InstructionSelector::VisitTailCall(Node* node) {
|
| // heuristics in the register allocator for where to emit constants.
|
| InitializeCallBuffer(node, &buffer, true, false);
|
|
|
| - DCHECK_EQ(0u, buffer.pushed_nodes.size());
|
| -
|
| // Select the appropriate opcode based on the call type.
|
| InstructionCode opcode;
|
| switch (descriptor->kind()) {
|
|
|