Move X8632-specific Assembler stuff to Machine Traits.

src/IceTargetLoweringX86BaseImpl.h

 //===- subzero/src/IceTargetLoweringX86BaseImpl.h - x86 lowering -*- C++ -*-==//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file implements the TargetLoweringX86Base class, which
@@ skipping 159 matching lines @@
 // optimization because it minimizes branches.
 template <class MachineTraits>
 bool BoolFolding<MachineTraits>::hasComplexLowering(const Inst *Instr) {
   switch (getProducerKind(Instr)) {
   default:
     return false;
   case PK_Icmp64:
     return true;
   case PK_Fcmp:
     return MachineTraits::TableFcmp[llvm::cast<InstFcmp>(Instr)->getCondition()]
-               .C2 != CondX86::Br_None;
+               .C2 != MachineTraits::Cond::Br_None;
   }
 }
 
 template <class MachineTraits>
 void BoolFolding<MachineTraits>::init(CfgNode *Node) {
   Producers.clear();
   for (Inst &Instr : Node->getInsts()) {
     // Check whether Instr is a valid producer.
     Variable *Var = Instr.getDest();
     if (!Instr.isDeleted() // only consider non-deleted instructions
@@ skipping 87 matching lines @@
   if (Func->getContext()->getFlags().getTargetInstructionSet() !=
       TargetInstructionSet::BaseInstructionSet) {
     InstructionSet = static_cast<typename Traits::InstructionSet>(
         (Func->getContext()->getFlags().getTargetInstructionSet() -
          TargetInstructionSet::X86InstructionSet_Begin) +
         Traits::InstructionSet::Begin);
   }
   // TODO: Don't initialize IntegerRegisters and friends every time.
   // Instead, initialize in some sort of static initializer for the
   // class.
-  llvm::SmallBitVector IntegerRegisters(RegX8632::Reg_NUM);
-  llvm::SmallBitVector IntegerRegistersI8(RegX8632::Reg_NUM);
-  llvm::SmallBitVector FloatRegisters(RegX8632::Reg_NUM);
-  llvm::SmallBitVector VectorRegisters(RegX8632::Reg_NUM);
-  llvm::SmallBitVector InvalidRegisters(RegX8632::Reg_NUM);
-  ScratchRegs.resize(RegX8632::Reg_NUM);
+  llvm::SmallBitVector IntegerRegisters(Traits::RegisterSet::Reg_NUM);
+  llvm::SmallBitVector IntegerRegistersI8(Traits::RegisterSet::Reg_NUM);
+  llvm::SmallBitVector FloatRegisters(Traits::RegisterSet::Reg_NUM);
+  llvm::SmallBitVector VectorRegisters(Traits::RegisterSet::Reg_NUM);
+  llvm::SmallBitVector InvalidRegisters(Traits::RegisterSet::Reg_NUM);
+  ScratchRegs.resize(Traits::RegisterSet::Reg_NUM);
 #define X(val, encode, name, name16, name8, scratch, preserved, stackptr,      \
           frameptr, isI8, isInt, isFP)                                         \
-  IntegerRegisters[RegX8632::val] = isInt;                                     \
-  IntegerRegistersI8[RegX8632::val] = isI8;                                    \
-  FloatRegisters[RegX8632::val] = isFP;                                        \
-  VectorRegisters[RegX8632::val] = isFP;                                       \
-  ScratchRegs[RegX8632::val] = scratch;
+  IntegerRegisters[Traits::RegisterSet::val] = isInt;                          \
+  IntegerRegistersI8[Traits::RegisterSet::val] = isI8;                         \
+  FloatRegisters[Traits::RegisterSet::val] = isFP;                             \
+  VectorRegisters[Traits::RegisterSet::val] = isFP;                            \
+  ScratchRegs[Traits::RegisterSet::val] = scratch;
   REGX8632_TABLE;
 #undef X
   TypeToRegisterSet[IceType_void] = InvalidRegisters;
   TypeToRegisterSet[IceType_i1] = IntegerRegistersI8;
   TypeToRegisterSet[IceType_i8] = IntegerRegistersI8;
   TypeToRegisterSet[IceType_i16] = IntegerRegisters;
   TypeToRegisterSet[IceType_i32] = IntegerRegisters;
   TypeToRegisterSet[IceType_i64] = IntegerRegisters;
   TypeToRegisterSet[IceType_f32] = FloatRegisters;
   TypeToRegisterSet[IceType_f64] = FloatRegisters;
@@ skipping 422 matching lines @@
   name,
     REGX8632_TABLE
 #undef X
 };
 
 template <class Machine>
 Variable *TargetX86Base<Machine>::getPhysicalRegister(SizeT RegNum, Type Ty) {
   if (Ty == IceType_void)
     Ty = IceType_i32;
   if (PhysicalRegisters[Ty].empty())
-    PhysicalRegisters[Ty].resize(RegX8632::Reg_NUM);
+    PhysicalRegisters[Ty].resize(Traits::RegisterSet::Reg_NUM);
   assert(RegNum < PhysicalRegisters[Ty].size());
   Variable *Reg = PhysicalRegisters[Ty][RegNum];
   if (Reg == nullptr) {
     Reg = Func->template makeVariable(Ty);
     Reg->setRegNum(RegNum);
     PhysicalRegisters[Ty][RegNum] = Reg;
     // Specially mark esp as an "argument" so that it is considered
     // live upon function entry.
-    if (RegNum == RegX8632::Reg_esp) {
+    if (RegNum == Traits::RegisterSet::Reg_esp) {
       Func->addImplicitArg(Reg);
       Reg->setIgnoreLiveness();
     }
   }
   return Reg;
 }
 
 template <class Machine>
 IceString TargetX86Base<Machine>::getRegName(SizeT RegNum, Type Ty) const {
-  assert(RegNum < RegX8632::Reg_NUM);
+  assert(RegNum < Traits::RegisterSet::Reg_NUM);
   static IceString RegNames8[] = {
 #define X(val, encode, name, name16, name8, scratch, preserved, stackptr,      \
           frameptr, isI8, isInt, isFP)                                         \
   name8,
       REGX8632_TABLE
 #undef X
   };
   static IceString RegNames16[] = {
 #define X(val, encode, name, name16, name8, scratch, preserved, stackptr,      \
           frameptr, isI8, isInt, isFP)                                         \
@@ skipping 25 matching lines @@
   int32_t Offset = Var->getStackOffset();
   if (!hasFramePointer())
     Offset += getStackAdjustment();
   if (Offset)
     Str << Offset;
   const Type FrameSPTy = IceType_i32;
   Str << "(%" << getRegName(getFrameOrStackReg(), FrameSPTy) << ")";
 }
 
 template <class Machine>
-X8632::Address
+typename TargetX86Base<Machine>::Traits::Address
 TargetX86Base<Machine>::stackVarToAsmOperand(const Variable *Var) const {
   if (Var->hasReg())
     llvm_unreachable("Stack Variable has a register assigned");
   if (Var->getWeight().isInf()) {
     llvm_unreachable("Infinite-weight Variable has no register assigned");
   }
   int32_t Offset = Var->getStackOffset();
   if (!hasFramePointer())
     Offset += getStackAdjustment();
-  return X8632::Address(RegX8632::getEncodedGPR(getFrameOrStackReg()), Offset);
+  return typename Traits::Address(
+      Traits::RegisterSet::getEncodedGPR(getFrameOrStackReg()), Offset);
 }
 
 template <class Machine> void TargetX86Base<Machine>::lowerArguments() {
   VarList &Args = Func->getArgs();
   // The first four arguments of vector type, regardless of their
   // position relative to the other arguments in the argument list, are
   // passed in registers xmm0 - xmm3.
   unsigned NumXmmArgs = 0;
 
   Context.init(Func->getEntryNode());
   Context.setInsertPoint(Context.getCur());
 
   for (SizeT I = 0, E = Args.size();
        I < E && NumXmmArgs < Traits::X86_MAX_XMM_ARGS; ++I) {
     Variable *Arg = Args[I];
     Type Ty = Arg->getType();
     if (!isVectorType(Ty))
       continue;
     // Replace Arg in the argument list with the home register.  Then
     // generate an instruction in the prolog to copy the home register
     // to the assigned location of Arg.
-    int32_t RegNum = RegX8632::Reg_xmm0 + NumXmmArgs;
+    int32_t RegNum = Traits::RegisterSet::Reg_xmm0 + NumXmmArgs;
     ++NumXmmArgs;
     Variable *RegisterArg = Func->template makeVariable(Ty);
     if (BuildDefs::dump())
       RegisterArg->setName(Func, "home_reg:" + Arg->getName(Func));
     RegisterArg->setRegNum(RegNum);
     RegisterArg->setIsArg();
     Arg->setIsArg(false);
 
     Args[I] = RegisterArg;
     Context.insert(InstAssign::create(Func, Arg, RegisterArg));
@@ skipping 139 matching lines @@
       _push(getPhysicalRegister(i));
     }
   }
   Ctx->statsUpdateRegistersSaved(NumCallee);
 
   // Generate "push ebp; mov ebp, esp"
   if (IsEbpBasedFrame) {
     assert((RegsUsed & getRegisterSet(RegSet_FramePointer, RegSet_None))
                .count() == 0);
     PreservedRegsSizeBytes += 4;
-    Variable *ebp = getPhysicalRegister(RegX8632::Reg_ebp);
-    Variable *esp = getPhysicalRegister(RegX8632::Reg_esp);
+    Variable *ebp = getPhysicalRegister(Traits::RegisterSet::Reg_ebp);
+    Variable *esp = getPhysicalRegister(Traits::RegisterSet::Reg_esp);
     _push(ebp);
     _mov(ebp, esp);
     // Keep ebp live for late-stage liveness analysis
     // (e.g. asm-verbose mode).
     Context.insert(InstFakeUse::create(Func, ebp));
   }
 
   // Align the variables area. SpillAreaPaddingBytes is the size of
   // the region after the preserved registers and before the spill areas.
   // LocalsSlotsPaddingBytes is the amount of padding between the globals
@@ skipping 14 matching lines @@
   if (NeedsStackAlignment) {
     uint32_t StackOffset =
         Traits::X86_RET_IP_SIZE_BYTES + PreservedRegsSizeBytes;
     uint32_t StackSize =
         Traits::applyStackAlignment(StackOffset + SpillAreaSizeBytes);
     SpillAreaSizeBytes = StackSize - StackOffset;
   }
 
   // Generate "sub esp, SpillAreaSizeBytes"
   if (SpillAreaSizeBytes)
-    _sub(getPhysicalRegister(RegX8632::Reg_esp),
+    _sub(getPhysicalRegister(Traits::RegisterSet::Reg_esp),
          Ctx->getConstantInt32(SpillAreaSizeBytes));
   Ctx->statsUpdateFrameBytes(SpillAreaSizeBytes);
 
   resetStackAdjustment();
 
   // Fill in stack offsets for stack args, and copy args into registers
   // for those that were register-allocated.  Args are pushed right to
   // left, so Arg[0] is closest to the stack/frame pointer.
   Variable *FramePtr = getPhysicalRegister(getFrameOrStackReg());
   size_t BasicFrameOffset =
@@ skipping 63 matching lines @@
   if (RI == E)
     return;
 
   // Convert the reverse_iterator position into its corresponding
   // (forward) iterator position.
   InstList::iterator InsertPoint = RI.base();
   --InsertPoint;
   Context.init(Node);
   Context.setInsertPoint(InsertPoint);
 
-  Variable *esp = getPhysicalRegister(RegX8632::Reg_esp);
+  Variable *esp = getPhysicalRegister(Traits::RegisterSet::Reg_esp);
   if (IsEbpBasedFrame) {
-    Variable *ebp = getPhysicalRegister(RegX8632::Reg_ebp);
+    Variable *ebp = getPhysicalRegister(Traits::RegisterSet::Reg_ebp);
     // For late-stage liveness analysis (e.g. asm-verbose mode),
     // adding a fake use of esp before the assignment of esp=ebp keeps
     // previous esp adjustments from being dead-code eliminated.
     Context.insert(InstFakeUse::create(Func, esp));
     _mov(esp, ebp);
     _pop(ebp);
   } else {
     // add esp, SpillAreaSizeBytes
     if (SpillAreaSizeBytes)
       _add(esp, Ctx->getConstantInt32(SpillAreaSizeBytes));
   }
 
   // Add pop instructions for preserved registers.
   llvm::SmallBitVector CalleeSaves =
       getRegisterSet(RegSet_CalleeSave, RegSet_None);
   for (SizeT i = 0; i < CalleeSaves.size(); ++i) {
     SizeT j = CalleeSaves.size() - i - 1;
-    if (j == RegX8632::Reg_ebp && IsEbpBasedFrame)
+    if (j == Traits::RegisterSet::Reg_ebp && IsEbpBasedFrame)
       continue;
     if (CalleeSaves[j] && RegsUsed[j]) {
       _pop(getPhysicalRegister(j));
     }
   }
 
   if (!Ctx->getFlags().getUseSandboxing())
     return;
   // Change the original ret instruction into a sandboxed return sequence.
   // t:ecx = pop
   // bundle_lock
   // and t, ~31
   // jmp *t
   // bundle_unlock
   // FakeUse <original_ret_operand>
   const SizeT BundleSize =
       1 << Func->template getAssembler<>()->getBundleAlignLog2Bytes();
-  Variable *T_ecx = makeReg(IceType_i32, RegX8632::Reg_ecx);
+  Variable *T_ecx = makeReg(IceType_i32, Traits::RegisterSet::Reg_ecx);
   _pop(T_ecx);
   _bundle_lock();
   _and(T_ecx, Ctx->getConstantInt32(~(BundleSize - 1)));
   _jmp(T_ecx);
   _bundle_unlock();
   if (RI->getSrcSize()) {
     Variable *RetValue = llvm::cast<Variable>(RI->getSrc(0));
     Context.insert(InstFakeUse::create(Func, RetValue));
   }
   RI->setDeleted();
@@ skipping 97 matching lines @@
     return legalize(MemOperand);
   }
   llvm_unreachable("Unsupported operand type");
   return nullptr;
 }
 
 template <class Machine>
 llvm::SmallBitVector
 TargetX86Base<Machine>::getRegisterSet(RegSetMask Include,
                                        RegSetMask Exclude) const {
-  llvm::SmallBitVector Registers(RegX8632::Reg_NUM);
+  llvm::SmallBitVector Registers(Traits::RegisterSet::Reg_NUM);
 
 #define X(val, encode, name, name16, name8, scratch, preserved, stackptr,      \
           frameptr, isI8, isInt, isFP)                                         \
   if (scratch && (Include & RegSet_CallerSave))                                \
-    Registers[RegX8632::val] = true;                                           \
+    Registers[Traits::RegisterSet::val] = true;                                \
   if (preserved && (Include & RegSet_CalleeSave))                              \
-    Registers[RegX8632::val] = true;                                           \
+    Registers[Traits::RegisterSet::val] = true;                                \
   if (stackptr && (Include & RegSet_StackPointer))                             \
-    Registers[RegX8632::val] = true;                                           \
+    Registers[Traits::RegisterSet::val] = true;                                \
   if (frameptr && (Include & RegSet_FramePointer))                             \
-    Registers[RegX8632::val] = true;                                           \
+    Registers[Traits::RegisterSet::val] = true;                                \
   if (scratch && (Exclude & RegSet_CallerSave))                                \
-    Registers[RegX8632::val] = false;                                          \
+    Registers[Traits::RegisterSet::val] = false;                               \
   if (preserved && (Exclude & RegSet_CalleeSave))                              \
-    Registers[RegX8632::val] = false;                                          \
+    Registers[Traits::RegisterSet::val] = false;                               \
   if (stackptr && (Exclude & RegSet_StackPointer))                             \
-    Registers[RegX8632::val] = false;                                          \
+    Registers[Traits::RegisterSet::val] = false;                               \
   if (frameptr && (Exclude & RegSet_FramePointer))                             \
-    Registers[RegX8632::val] = false;
+    Registers[Traits::RegisterSet::val] = false;
 
   REGX8632_TABLE
 
 #undef X
 
   return Registers;
 }
 
 template <class Machine>
 void TargetX86Base<Machine>::lowerAlloca(const InstAlloca *Inst) {
   IsEbpBasedFrame = true;
   // Conservatively require the stack to be aligned.  Some stack
   // adjustment operations implemented below assume that the stack is
   // aligned before the alloca.  All the alloca code ensures that the
   // stack alignment is preserved after the alloca.  The stack alignment
   // restriction can be relaxed in some cases.
   NeedsStackAlignment = true;
 
   // TODO(stichnot): minimize the number of adjustments of esp, etc.
-  Variable *esp = getPhysicalRegister(RegX8632::Reg_esp);
+  Variable *esp = getPhysicalRegister(Traits::RegisterSet::Reg_esp);
   Operand *TotalSize = legalize(Inst->getSizeInBytes());
   Variable *Dest = Inst->getDest();
   uint32_t AlignmentParam = Inst->getAlignInBytes();
   // For default align=0, set it to the real value 1, to avoid any
   // bit-manipulation problems below.
   AlignmentParam = std::max(AlignmentParam, 1u);
 
   // LLVM enforces power of 2 alignment.
   assert(llvm::isPowerOf2_32(AlignmentParam));
   assert(llvm::isPowerOf2_32(Traits::X86_STACK_ALIGNMENT_BYTES));
@@ skipping 218 matching lines @@
     case InstArithmetic::Sub:
       _mov(T_Lo, Src0Lo);
       _sub(T_Lo, Src1Lo);
       _mov(DestLo, T_Lo);
       _mov(T_Hi, Src0Hi);
       _sbb(T_Hi, Src1Hi);
       _mov(DestHi, T_Hi);
       break;
     case InstArithmetic::Mul: {
       Variable *T_1 = nullptr, *T_2 = nullptr, *T_3 = nullptr;
-      Variable *T_4Lo = makeReg(IceType_i32, RegX8632::Reg_eax);
-      Variable *T_4Hi = makeReg(IceType_i32, RegX8632::Reg_edx);
+      Variable *T_4Lo = makeReg(IceType_i32, Traits::RegisterSet::Reg_eax);
+      Variable *T_4Hi = makeReg(IceType_i32, Traits::RegisterSet::Reg_edx);
       // gcc does the following:
       // a=b*c ==>
       //   t1 = b.hi; t1 *=(imul) c.lo
       //   t2 = c.hi; t2 *=(imul) b.lo
       //   t3:eax = b.lo
       //   t4.hi:edx,t4.lo:eax = t3:eax *(mul) c.lo
       //   a.lo = t4.lo
       //   t4.hi += t1
       //   t4.hi += t2
       //   a.hi = t4.hi
       // The mul instruction cannot take an immediate operand.
       Src1Lo = legalize(Src1Lo, Legal_Reg | Legal_Mem);
       _mov(T_1, Src0Hi);
       _imul(T_1, Src1Lo);
       _mov(T_2, Src1Hi);
       _imul(T_2, Src0Lo);
-      _mov(T_3, Src0Lo, RegX8632::Reg_eax);
+      _mov(T_3, Src0Lo, Traits::RegisterSet::Reg_eax);
       _mul(T_4Lo, T_3, Src1Lo);
       // The mul instruction produces two dest variables, edx:eax.  We
       // create a fake definition of edx to account for this.
       Context.insert(InstFakeDef::create(Func, T_4Hi, T_4Lo));
       _mov(DestLo, T_4Lo);
       _add(T_4Hi, T_1);
       _add(T_4Hi, T_2);
       _mov(DestHi, T_4Hi);
     } break;
     case InstArithmetic::Shl: {
@@ skipping 10 matching lines @@
       //   use(t3)
       //   t3 = t2
       //   t2 = 0
       // L1:
       //   a.lo = t2
       //   a.hi = t3
       Variable *T_1 = nullptr, *T_2 = nullptr, *T_3 = nullptr;
       Constant *BitTest = Ctx->getConstantInt32(0x20);
       Constant *Zero = Ctx->getConstantZero(IceType_i32);
       InstX8632Label *Label = InstX8632Label::create(Func, this);
-      _mov(T_1, Src1Lo, RegX8632::Reg_ecx);
+      _mov(T_1, Src1Lo, Traits::RegisterSet::Reg_ecx);
       _mov(T_2, Src0Lo);
       _mov(T_3, Src0Hi);
       _shld(T_3, T_2, T_1);
       _shl(T_2, T_1);
       _test(T_1, BitTest);
-      _br(CondX86::Br_e, Label);
+      _br(Traits::Cond::Br_e, Label);
       // T_2 and T_3 are being assigned again because of the
       // intra-block control flow, so we need the _mov_nonkillable
       // variant to avoid liveness problems.
       _mov_nonkillable(T_3, T_2);
       _mov_nonkillable(T_2, Zero);
       Context.insert(Label);
       _mov(DestLo, T_2);
       _mov(DestHi, T_3);
     } break;
     case InstArithmetic::Lshr: {
       // a=b>>c (unsigned) ==>
       //   t1:ecx = c.lo & 0xff
       //   t2 = b.lo
       //   t3 = b.hi
       //   t2 = shrd t2, t3, t1
       //   t3 = shr t3, t1
       //   test t1, 0x20
       //   je L1
       //   use(t2)
       //   t2 = t3
       //   t3 = 0
       // L1:
       //   a.lo = t2
       //   a.hi = t3
       Variable *T_1 = nullptr, *T_2 = nullptr, *T_3 = nullptr;
       Constant *BitTest = Ctx->getConstantInt32(0x20);
       Constant *Zero = Ctx->getConstantZero(IceType_i32);
       InstX8632Label *Label = InstX8632Label::create(Func, this);
-      _mov(T_1, Src1Lo, RegX8632::Reg_ecx);
+      _mov(T_1, Src1Lo, Traits::RegisterSet::Reg_ecx);
       _mov(T_2, Src0Lo);
       _mov(T_3, Src0Hi);
       _shrd(T_2, T_3, T_1);
       _shr(T_3, T_1);
       _test(T_1, BitTest);
-      _br(CondX86::Br_e, Label);
+      _br(Traits::Cond::Br_e, Label);
       // T_2 and T_3 are being assigned again because of the
       // intra-block control flow, so we need the _mov_nonkillable
       // variant to avoid liveness problems.
       _mov_nonkillable(T_2, T_3);
       _mov_nonkillable(T_3, Zero);
       Context.insert(Label);
       _mov(DestLo, T_2);
       _mov(DestHi, T_3);
     } break;
     case InstArithmetic::Ashr: {
       // a=b>>c (signed) ==>
       //   t1:ecx = c.lo & 0xff
       //   t2 = b.lo
       //   t3 = b.hi
       //   t2 = shrd t2, t3, t1
       //   t3 = sar t3, t1
       //   test t1, 0x20
       //   je L1
       //   use(t2)
       //   t2 = t3
       //   t3 = sar t3, 0x1f
       // L1:
       //   a.lo = t2
       //   a.hi = t3
       Variable *T_1 = nullptr, *T_2 = nullptr, *T_3 = nullptr;
       Constant *BitTest = Ctx->getConstantInt32(0x20);
       Constant *SignExtend = Ctx->getConstantInt32(0x1f);
       InstX8632Label *Label = InstX8632Label::create(Func, this);
-      _mov(T_1, Src1Lo, RegX8632::Reg_ecx);
+      _mov(T_1, Src1Lo, Traits::RegisterSet::Reg_ecx);
       _mov(T_2, Src0Lo);
       _mov(T_3, Src0Hi);
       _shrd(T_2, T_3, T_1);
       _sar(T_3, T_1);
       _test(T_1, BitTest);
-      _br(CondX86::Br_e, Label);
+      _br(Traits::Cond::Br_e, Label);
       // T_2 and T_3 are being assigned again because of the
       // intra-block control flow, so T_2 needs the _mov_nonkillable
       // variant to avoid liveness problems.  T_3 doesn't need special
       // treatment because it is reassigned via _sar instead of _mov.
       _mov_nonkillable(T_2, T_3);
       _sar(T_3, SignExtend);
       Context.insert(Label);
       _mov(DestLo, T_2);
       _mov(DestHi, T_3);
     } break;
@@ skipping 50 matching lines @@
     case InstArithmetic::Sub: {
       Variable *T = makeReg(Dest->getType());
       _movp(T, Src0);
       _psub(T, Src1);
       _movp(Dest, T);
     } break;
     case InstArithmetic::Mul: {
       bool TypesAreValidForPmull =
           Dest->getType() == IceType_v4i32 || Dest->getType() == IceType_v8i16;
       bool InstructionSetIsValidForPmull =
-          Dest->getType() == IceType_v8i16 || InstructionSet >= Machine::SSE4_1;
+          Dest->getType() == IceType_v8i16 || InstructionSet >= Traits::SSE4_1;
       if (TypesAreValidForPmull && InstructionSetIsValidForPmull) {
         Variable *T = makeReg(Dest->getType());
         _movp(T, Src0);
         _pmull(T, Src1);
         _movp(Dest, T);
       } else if (Dest->getType() == IceType_v4i32) {
         // Lowering sequence:
         // Note: The mask arguments have index 0 on the left.
         //
         // movups  T1, Src0
@@ skipping 106 matching lines @@
     _mov(Dest, T);
     break;
   case InstArithmetic::Mul:
     if (auto *C = llvm::dyn_cast<ConstantInteger32>(Src1)) {
       if (optimizeScalarMul(Dest, Src0, C->getValue()))
         return;
     }
     // The 8-bit version of imul only allows the form "imul r/m8"
     // where T must be in eax.
     if (isByteSizedArithType(Dest->getType())) {
-      _mov(T, Src0, RegX8632::Reg_eax);
+      _mov(T, Src0, Traits::RegisterSet::Reg_eax);
       Src1 = legalize(Src1, Legal_Reg | Legal_Mem);
     } else {
       _mov(T, Src0);
     }
     _imul(T, Src1);
     _mov(Dest, T);
     break;
   case InstArithmetic::Shl:
     _mov(T, Src0);
     if (!llvm::isa<Constant>(Src1))
-      Src1 = legalizeToVar(Src1, RegX8632::Reg_ecx);
+      Src1 = legalizeToVar(Src1, Traits::RegisterSet::Reg_ecx);
     _shl(T, Src1);
     _mov(Dest, T);
     break;
   case InstArithmetic::Lshr:
     _mov(T, Src0);
     if (!llvm::isa<Constant>(Src1))
-      Src1 = legalizeToVar(Src1, RegX8632::Reg_ecx);
+      Src1 = legalizeToVar(Src1, Traits::RegisterSet::Reg_ecx);
     _shr(T, Src1);
     _mov(Dest, T);
     break;
   case InstArithmetic::Ashr:
     _mov(T, Src0);
     if (!llvm::isa<Constant>(Src1))
-      Src1 = legalizeToVar(Src1, RegX8632::Reg_ecx);
+      Src1 = legalizeToVar(Src1, Traits::RegisterSet::Reg_ecx);
     _sar(T, Src1);
     _mov(Dest, T);
     break;
   case InstArithmetic::Udiv:
     // div and idiv are the few arithmetic operators that do not allow
     // immediates as the operand.
     Src1 = legalize(Src1, Legal_Reg | Legal_Mem);
     if (isByteSizedArithType(Dest->getType())) {
       Variable *T_ah = nullptr;
       Constant *Zero = Ctx->getConstantZero(IceType_i8);
-      _mov(T, Src0, RegX8632::Reg_eax);
-      _mov(T_ah, Zero, RegX8632::Reg_ah);
+      _mov(T, Src0, Traits::RegisterSet::Reg_eax);
+      _mov(T_ah, Zero, Traits::RegisterSet::Reg_ah);
       _div(T, Src1, T_ah);
       _mov(Dest, T);
     } else {
       Constant *Zero = Ctx->getConstantZero(IceType_i32);
-      _mov(T, Src0, RegX8632::Reg_eax);
-      _mov(T_edx, Zero, RegX8632::Reg_edx);
+      _mov(T, Src0, Traits::RegisterSet::Reg_eax);
+      _mov(T_edx, Zero, Traits::RegisterSet::Reg_edx);
       _div(T, Src1, T_edx);
       _mov(Dest, T);
     }
     break;
   case InstArithmetic::Sdiv:
     // TODO(stichnot): Enable this after doing better performance
     // and cross testing.
     if (false && Ctx->getFlags().getOptLevel() >= Opt_1) {
       // Optimize division by constant power of 2, but not for Om1
       // or O0, just to keep things simple there.
@@ skipping 22 matching lines @@
             _add(T, Src0);
             _sar(T, Ctx->getConstantInt(Ty, LogDiv));
           }
           _mov(Dest, T);
           return;
         }
       }
     }
     Src1 = legalize(Src1, Legal_Reg | Legal_Mem);
     if (isByteSizedArithType(Dest->getType())) {
-      _mov(T, Src0, RegX8632::Reg_eax);
+      _mov(T, Src0, Traits::RegisterSet::Reg_eax);
       _cbwdq(T, T);
       _idiv(T, Src1, T);
       _mov(Dest, T);
     } else {
-      T_edx = makeReg(IceType_i32, RegX8632::Reg_edx);
-      _mov(T, Src0, RegX8632::Reg_eax);
+      T_edx = makeReg(IceType_i32, Traits::RegisterSet::Reg_edx);
+      _mov(T, Src0, Traits::RegisterSet::Reg_eax);
       _cbwdq(T_edx, T);
       _idiv(T, Src1, T_edx);
       _mov(Dest, T);
     }
     break;
   case InstArithmetic::Urem:
     Src1 = legalize(Src1, Legal_Reg | Legal_Mem);
     if (isByteSizedArithType(Dest->getType())) {
       Variable *T_ah = nullptr;
       Constant *Zero = Ctx->getConstantZero(IceType_i8);
-      _mov(T, Src0, RegX8632::Reg_eax);
-      _mov(T_ah, Zero, RegX8632::Reg_ah);
+      _mov(T, Src0, Traits::RegisterSet::Reg_eax);
+      _mov(T_ah, Zero, Traits::RegisterSet::Reg_ah);
       _div(T_ah, Src1, T);
       _mov(Dest, T_ah);
     } else {
       Constant *Zero = Ctx->getConstantZero(IceType_i32);
-      _mov(T_edx, Zero, RegX8632::Reg_edx);
-      _mov(T, Src0, RegX8632::Reg_eax);
+      _mov(T_edx, Zero, Traits::RegisterSet::Reg_edx);
+      _mov(T, Src0, Traits::RegisterSet::Reg_eax);
       _div(T_edx, Src1, T);
       _mov(Dest, T_edx);
     }
     break;
   case InstArithmetic::Srem:
     // TODO(stichnot): Enable this after doing better performance
     // and cross testing.
     if (false && Ctx->getFlags().getOptLevel() >= Opt_1) {
       // Optimize mod by constant power of 2, but not for Om1 or O0,
       // just to keep things simple there.
@@ skipping 27 matching lines @@
           _and(T, Ctx->getConstantInt(Ty, -(1 << LogDiv)));
           _sub(T, Src0);
           _neg(T);
           _mov(Dest, T);
           return;
         }
       }
     }
     Src1 = legalize(Src1, Legal_Reg | Legal_Mem);
     if (isByteSizedArithType(Dest->getType())) {
-      Variable *T_ah = makeReg(IceType_i8, RegX8632::Reg_ah);
-      _mov(T, Src0, RegX8632::Reg_eax);
+      Variable *T_ah = makeReg(IceType_i8, Traits::RegisterSet::Reg_ah);
+      _mov(T, Src0, Traits::RegisterSet::Reg_eax);
       _cbwdq(T, T);
       Context.insert(InstFakeDef::create(Func, T_ah));
       _idiv(T_ah, Src1, T);
       _mov(Dest, T_ah);
     } else {
-      T_edx = makeReg(IceType_i32, RegX8632::Reg_edx);
-      _mov(T, Src0, RegX8632::Reg_eax);
+      T_edx = makeReg(IceType_i32, Traits::RegisterSet::Reg_edx);
+      _mov(T, Src0, Traits::RegisterSet::Reg_eax);
       _cbwdq(T_edx, T);
       _idiv(T_edx, Src1, T);
       _mov(Dest, T_edx);
     }
     break;
   case InstArithmetic::Fadd:
     _mov(T, Src0);
     _addss(T, Src1);
     _mov(Dest, T);
     break;
@@ skipping 95 matching lines @@
       _br(Traits::getIcmp32Mapping(Cmp->getCondition()), Inst->getTargetTrue(),
           Inst->getTargetFalse());
       return;
     }
     }
   }
 
   Operand *Src0 = legalize(Cond, Legal_Reg | Legal_Mem);
   Constant *Zero = Ctx->getConstantZero(IceType_i32);
   _cmp(Src0, Zero);
-  _br(CondX86::Br_ne, Inst->getTargetTrue(), Inst->getTargetFalse());
+  _br(Traits::Cond::Br_ne, Inst->getTargetTrue(), Inst->getTargetFalse());
 }
 
 template <class Machine>
 void TargetX86Base<Machine>::lowerCall(const InstCall *Instr) {
   // x86-32 calling convention:
   //
   // * At the point before the call, the stack must be aligned to 16
   // bytes.
   //
   // * The first four arguments of vector type, regardless of their
@@ skipping 26 matching lines @@
     // The PNaCl ABI requires the width of arguments to be at least 32 bits.
     assert(typeWidthInBytes(Ty) >= 4);
     if (isVectorType(Ty) && XmmArgs.size() < Traits::X86_MAX_XMM_ARGS) {
       XmmArgs.push_back(Arg);
     } else {
       StackArgs.push_back(Arg);
       if (isVectorType(Arg->getType())) {
         ParameterAreaSizeBytes =
             Traits::applyStackAlignment(ParameterAreaSizeBytes);
       }
-      Variable *esp = Func->getTarget()->getPhysicalRegister(RegX8632::Reg_esp);
+      Variable *esp =
+          Func->getTarget()->getPhysicalRegister(Traits::RegisterSet::Reg_esp);
       Constant *Loc = Ctx->getConstantInt32(ParameterAreaSizeBytes);
       StackArgLocations.push_back(OperandX8632Mem::create(Func, Ty, esp, Loc));
       ParameterAreaSizeBytes += typeWidthInBytesOnStack(Arg->getType());
     }
   }
 
   // Adjust the parameter area so that the stack is aligned.  It is
   // assumed that the stack is already aligned at the start of the
   // calling sequence.
   ParameterAreaSizeBytes = Traits::applyStackAlignment(ParameterAreaSizeBytes);
@@ skipping 17 matching lines @@
   // Copy arguments to be passed in registers to the appropriate
   // registers.
   // TODO: Investigate the impact of lowering arguments passed in
   // registers after lowering stack arguments as opposed to the other
   // way around.  Lowering register arguments after stack arguments may
   // reduce register pressure.  On the other hand, lowering register
   // arguments first (before stack arguments) may result in more compact
   // code, as the memory operand displacements may end up being smaller
   // before any stack adjustment is done.
   for (SizeT i = 0, NumXmmArgs = XmmArgs.size(); i < NumXmmArgs; ++i) {
-    Variable *Reg = legalizeToVar(XmmArgs[i], RegX8632::Reg_xmm0 + i);
+    Variable *Reg =
+        legalizeToVar(XmmArgs[i], Traits::RegisterSet::Reg_xmm0 + i);
     // Generate a FakeUse of register arguments so that they do not get
     // dead code eliminated as a result of the FakeKill of scratch
     // registers after the call.
     Context.insert(InstFakeUse::create(Func, Reg));
   }
   // Generate the call instruction.  Assign its result to a temporary
   // with high register allocation weight.
   Variable *Dest = Instr->getDest();
   // ReturnReg doubles as ReturnRegLo as necessary.
   Variable *ReturnReg = nullptr;
   Variable *ReturnRegHi = nullptr;
   if (Dest) {
     switch (Dest->getType()) {
     case IceType_NUM:
       llvm_unreachable("Invalid Call dest type");
       break;
     case IceType_void:
       break;
     case IceType_i1:
     case IceType_i8:
     case IceType_i16:
     case IceType_i32:
-      ReturnReg = makeReg(Dest->getType(), RegX8632::Reg_eax);
+      ReturnReg = makeReg(Dest->getType(), Traits::RegisterSet::Reg_eax);
       break;
     case IceType_i64:
-      ReturnReg = makeReg(IceType_i32, RegX8632::Reg_eax);
-      ReturnRegHi = makeReg(IceType_i32, RegX8632::Reg_edx);
+      ReturnReg = makeReg(IceType_i32, Traits::RegisterSet::Reg_eax);
+      ReturnRegHi = makeReg(IceType_i32, Traits::RegisterSet::Reg_edx);
       break;
     case IceType_f32:
     case IceType_f64:
       // Leave ReturnReg==ReturnRegHi==nullptr, and capture the result with
       // the fstp instruction.
       break;
     case IceType_v4i1:
     case IceType_v8i1:
     case IceType_v16i1:
     case IceType_v16i8:
     case IceType_v8i16:
     case IceType_v4i32:
     case IceType_v4f32:
-      ReturnReg = makeReg(Dest->getType(), RegX8632::Reg_xmm0);
+      ReturnReg = makeReg(Dest->getType(), Traits::RegisterSet::Reg_xmm0);
       break;
     }
   }
   Operand *CallTarget = legalize(Instr->getCallTarget());
   const bool NeedSandboxing = Ctx->getFlags().getUseSandboxing();
   if (NeedSandboxing) {
     if (llvm::isa<Constant>(CallTarget)) {
       _bundle_lock(InstBundleLock::Opt_AlignToEnd);
     } else {
       Variable *CallTargetVar = nullptr;
       _mov(CallTargetVar, CallTarget);
       _bundle_lock(InstBundleLock::Opt_AlignToEnd);
       const SizeT BundleSize =
           1 << Func->template getAssembler<>()->getBundleAlignLog2Bytes();
       _and(CallTargetVar, Ctx->getConstantInt32(~(BundleSize - 1)));
       CallTarget = CallTargetVar;
     }
   }
   Inst *NewCall = InstX8632Call::create(Func, ReturnReg, CallTarget);
   Context.insert(NewCall);
   if (NeedSandboxing)
     _bundle_unlock();
   if (ReturnRegHi)
     Context.insert(InstFakeDef::create(Func, ReturnRegHi));
 
   // Add the appropriate offset to esp.  The call instruction takes care
   // of resetting the stack offset during emission.
   if (ParameterAreaSizeBytes) {
-    Variable *esp = Func->getTarget()->getPhysicalRegister(RegX8632::Reg_esp);
+    Variable *esp =
+        Func->getTarget()->getPhysicalRegister(Traits::RegisterSet::Reg_esp);
     _add(esp, Ctx->getConstantInt32(ParameterAreaSizeBytes));
   }
 
   // Insert a register-kill pseudo instruction.
   Context.insert(InstFakeKill::create(Func, NewCall));
 
   // Generate a FakeUse to keep the call live if necessary.
   if (Instr->hasSideEffects() && ReturnReg) {
     Inst *FakeUse = InstFakeUse::create(Func, ReturnReg);
     Context.insert(FakeUse);
@@ skipping 518 matching lines @@
   assert(ElementIndex);
 
   unsigned Index = ElementIndex->getValue();
   Type Ty = SourceVectNotLegalized->getType();
   Type ElementTy = typeElementType(Ty);
   Type InVectorElementTy = Traits::getInVectorElementType(Ty);
   Variable *ExtractedElementR = makeReg(InVectorElementTy);
 
   // TODO(wala): Determine the best lowering sequences for each type.
   bool CanUsePextr = Ty == IceType_v8i16 || Ty == IceType_v8i1 ||
-                     InstructionSet >= Machine::SSE4_1;
+                     InstructionSet >= Traits::SSE4_1;
   if (CanUsePextr && Ty != IceType_v4f32) {
     // Use pextrb, pextrw, or pextrd.
     Constant *Mask = Ctx->getConstantInt32(Index);
     Variable *SourceVectR = legalizeToVar(SourceVectNotLegalized);
     _pextr(ExtractedElementR, SourceVectR, Mask);
   } else if (Ty == IceType_v4i32 || Ty == IceType_v4f32 || Ty == IceType_v4i1) {
     // Use pshufd and movd/movss.
     Variable *T = nullptr;
     if (Index) {
       // The shuffle only needs to occur if the element to be extracted
@@ skipping 72 matching lines @@
     } else if (Condition == InstFcmp::False) {
       T = makeVectorOfZeros(Dest->getType());
     } else {
       Operand *Src0RM = legalize(Src0, Legal_Reg | Legal_Mem);
       Operand *Src1RM = legalize(Src1, Legal_Reg | Legal_Mem);
       if (llvm::isa<OperandX8632Mem>(Src1RM))
         Src1RM = legalizeToVar(Src1RM);
 
       switch (Condition) {
       default: {
-        CondX86::CmppsCond Predicate = Traits::TableFcmp[Index].Predicate;
-        assert(Predicate != CondX86::Cmpps_Invalid);
+        typename Traits::Cond::CmppsCond Predicate =
+            Traits::TableFcmp[Index].Predicate;
+        assert(Predicate != Traits::Cond::Cmpps_Invalid);
         T = makeReg(Src0RM->getType());
         _movp(T, Src0RM);
         _cmpps(T, Src1RM, Predicate);
       } break;
       case InstFcmp::One: {
         // Check both unequal and ordered.
         T = makeReg(Src0RM->getType());
         Variable *T2 = makeReg(Src0RM->getType());
         _movp(T, Src0RM);
-        _cmpps(T, Src1RM, CondX86::Cmpps_neq);
+        _cmpps(T, Src1RM, Traits::Cond::Cmpps_neq);
         _movp(T2, Src0RM);
-        _cmpps(T2, Src1RM, CondX86::Cmpps_ord);
+        _cmpps(T2, Src1RM, Traits::Cond::Cmpps_ord);
         _pand(T, T2);
       } break;
       case InstFcmp::Ueq: {
         // Check both equal or unordered.
         T = makeReg(Src0RM->getType());
         Variable *T2 = makeReg(Src0RM->getType());
         _movp(T, Src0RM);
-        _cmpps(T, Src1RM, CondX86::Cmpps_eq);
+        _cmpps(T, Src1RM, Traits::Cond::Cmpps_eq);
         _movp(T2, Src0RM);
-        _cmpps(T2, Src1RM, CondX86::Cmpps_unord);
+        _cmpps(T2, Src1RM, Traits::Cond::Cmpps_unord);
         _por(T, T2);
       } break;
       }
     }
 
     _movp(Dest, T);
     eliminateNextVectorSextInstruction(Dest);
     return;
   }
 
   // Lowering a = fcmp cond, b, c
   //   ucomiss b, c       /* only if C1 != Br_None */
   //                      /* but swap b,c order if SwapOperands==true */
   //   mov a, <default>
   //   j<C1> label        /* only if C1 != Br_None */
   //   j<C2> label        /* only if C2 != Br_None */
   //   FakeUse(a)         /* only if C1 != Br_None */
   //   mov a, !<default>  /* only if C1 != Br_None */
   //   label:             /* only if C1 != Br_None */
   //
   // setcc lowering when C1 != Br_None && C2 == Br_None:
   //   ucomiss b, c       /* but swap b,c order if SwapOperands==true */
   //   setcc a, C1
   InstFcmp::FCond Condition = Inst->getCondition();
   size_t Index = static_cast<size_t>(Condition);
   assert(Index < Traits::TableFcmpSize);
   if (Traits::TableFcmp[Index].SwapScalarOperands)
     std::swap(Src0, Src1);
-  bool HasC1 = (Traits::TableFcmp[Index].C1 != CondX86::Br_None);
-  bool HasC2 = (Traits::TableFcmp[Index].C2 != CondX86::Br_None);
+  bool HasC1 = (Traits::TableFcmp[Index].C1 != Traits::Cond::Br_None);
+  bool HasC2 = (Traits::TableFcmp[Index].C2 != Traits::Cond::Br_None);
   if (HasC1) {
     Src0 = legalize(Src0);
     Operand *Src1RM = legalize(Src1, Legal_Reg | Legal_Mem);
     Variable *T = nullptr;
     _mov(T, Src0);
     _ucomiss(T, Src1RM);
     if (!HasC2) {
       assert(Traits::TableFcmp[Index].Default);
       _setcc(Dest, Traits::TableFcmp[Index].C1);
       return;
@@ skipping 137 matching lines @@
     Operand *Src0LoRM = legalize(loOperand(Src0), Legal_Reg | Legal_Mem);
     Operand *Src0HiRM = legalize(hiOperand(Src0), Legal_Reg | Legal_Mem);
     Operand *Src1LoRI = legalize(loOperand(Src1), Legal_Reg | Legal_Imm);
     Operand *Src1HiRI = legalize(hiOperand(Src1), Legal_Reg | Legal_Imm);
     Constant *Zero = Ctx->getConstantZero(IceType_i32);
     Constant *One = Ctx->getConstantInt32(1);
     InstX8632Label *LabelFalse = InstX8632Label::create(Func, this);
     InstX8632Label *LabelTrue = InstX8632Label::create(Func, this);
     _mov(Dest, One);
     _cmp(Src0HiRM, Src1HiRI);
-    if (Traits::TableIcmp64[Index].C1 != CondX86::Br_None)
+    if (Traits::TableIcmp64[Index].C1 != Traits::Cond::Br_None)
       _br(Traits::TableIcmp64[Index].C1, LabelTrue);
-    if (Traits::TableIcmp64[Index].C2 != CondX86::Br_None)
+    if (Traits::TableIcmp64[Index].C2 != Traits::Cond::Br_None)
       _br(Traits::TableIcmp64[Index].C2, LabelFalse);
     _cmp(Src0LoRM, Src1LoRI);
     _br(Traits::TableIcmp64[Index].C3, LabelTrue);
     Context.insert(LabelFalse);
     _mov_nonkillable(Dest, Zero);
     Context.insert(LabelTrue);
     return;
   }
 
   // cmp b, c
@@ skipping 21 matching lines @@
     // Expand the element to the appropriate size for it to be inserted
     // in the vector.
     Variable *Expanded = Func->template makeVariable(InVectorElementTy);
     InstCast *Cast = InstCast::create(Func, InstCast::Zext, Expanded,
                                       ElementToInsertNotLegalized);
     lowerCast(Cast);
     ElementToInsertNotLegalized = Expanded;
   }
 
   if (Ty == IceType_v8i16 || Ty == IceType_v8i1 ||
-      InstructionSet >= Machine::SSE4_1) {
+      InstructionSet >= Traits::SSE4_1) {
     // Use insertps, pinsrb, pinsrw, or pinsrd.
     Operand *ElementRM =
         legalize(ElementToInsertNotLegalized, Legal_Reg | Legal_Mem);
     Operand *SourceVectRM =
         legalize(SourceVectNotLegalized, Legal_Reg | Legal_Mem);
     Variable *T = makeReg(Ty);
     _movp(T, SourceVectRM);
     if (Ty == IceType_v4f32)
       _insertps(T, ElementRM, Ctx->getConstantInt32(Index << 4));
     else
@@ skipping 393 matching lines @@
   }
   case Intrinsics::Sqrt: {
     Operand *Src = legalize(Instr->getArg(0));
     Variable *Dest = Instr->getDest();
     Variable *T = makeReg(Dest->getType());
     _sqrtss(T, Src);
     _mov(Dest, T);
     return;
   }
   case Intrinsics::Stacksave: {
-    Variable *esp = Func->getTarget()->getPhysicalRegister(RegX8632::Reg_esp);
+    Variable *esp =
+        Func->getTarget()->getPhysicalRegister(Traits::RegisterSet::Reg_esp);
     Variable *Dest = Instr->getDest();
     _mov(Dest, esp);
     return;
   }
   case Intrinsics::Stackrestore: {
-    Variable *esp = Func->getTarget()->getPhysicalRegister(RegX8632::Reg_esp);
+    Variable *esp =
+        Func->getTarget()->getPhysicalRegister(Traits::RegisterSet::Reg_esp);
     _mov_nonkillable(esp, Instr->getArg(0));
     return;
   }
   case Intrinsics::Trap:
     _ud2();
     return;
   case Intrinsics::UnknownIntrinsic:
     Func->setError("Should not be lowering UnknownIntrinsic");
     return;
   }
   return;
 }
 
 template <class Machine>
 void TargetX86Base<Machine>::lowerAtomicCmpxchg(Variable *DestPrev,
                                                 Operand *Ptr, Operand *Expected,
                                                 Operand *Desired) {
   if (Expected->getType() == IceType_i64) {
     // Reserve the pre-colored registers first, before adding any more
     // infinite-weight variables from formMemoryOperand's legalization.
-    Variable *T_edx = makeReg(IceType_i32, RegX8632::Reg_edx);
-    Variable *T_eax = makeReg(IceType_i32, RegX8632::Reg_eax);
-    Variable *T_ecx = makeReg(IceType_i32, RegX8632::Reg_ecx);
-    Variable *T_ebx = makeReg(IceType_i32, RegX8632::Reg_ebx);
+    Variable *T_edx = makeReg(IceType_i32, Traits::RegisterSet::Reg_edx);
+    Variable *T_eax = makeReg(IceType_i32, Traits::RegisterSet::Reg_eax);
+    Variable *T_ecx = makeReg(IceType_i32, Traits::RegisterSet::Reg_ecx);
+    Variable *T_ebx = makeReg(IceType_i32, Traits::RegisterSet::Reg_ebx);
     _mov(T_eax, loOperand(Expected));
     _mov(T_edx, hiOperand(Expected));
     _mov(T_ebx, loOperand(Desired));
     _mov(T_ecx, hiOperand(Desired));
     OperandX8632Mem *Addr = formMemoryOperand(Ptr, Expected->getType());
     const bool Locked = true;
     _cmpxchg8b(Addr, T_edx, T_eax, T_ecx, T_ebx, Locked);
     Variable *DestLo = llvm::cast<Variable>(loOperand(DestPrev));
     Variable *DestHi = llvm::cast<Variable>(hiOperand(DestPrev));
     _mov(DestLo, T_eax);
     _mov(DestHi, T_edx);
     return;
   }
-  Variable *T_eax = makeReg(Expected->getType(), RegX8632::Reg_eax);
+  Variable *T_eax = makeReg(Expected->getType(), Traits::RegisterSet::Reg_eax);
   _mov(T_eax, Expected);
   OperandX8632Mem *Addr = formMemoryOperand(Ptr, Expected->getType());
   Variable *DesiredReg = legalizeToVar(Desired);
   const bool Locked = true;
   _cmpxchg(Addr, T_eax, DesiredReg, Locked);
   _mov(DestPrev, T_eax);
 }
 
 template <class Machine>
 bool TargetX86Base<Machine>::tryOptimizedCmpxchgCmpBr(Variable *Dest,
@@ skipping 50 matching lines @@
           NextBr->isLastUse(NextCmp->getDest())) {
         lowerAtomicCmpxchg(Dest, PtrToMem, Expected, Desired);
         for (size_t i = 0; i < PhiAssigns.size(); ++i) {
           // Lower the phi assignments now, before the branch (same placement
           // as before).
           InstAssign *PhiAssign = PhiAssigns[i];
           PhiAssign->setDeleted();
           lowerAssign(PhiAssign);
           Context.advanceNext();
         }
-        _br(CondX86::Br_e, NextBr->getTargetTrue(), NextBr->getTargetFalse());
+        _br(Traits::Cond::Br_e, NextBr->getTargetTrue(),
+            NextBr->getTargetFalse());
         // Skip over the old compare and branch, by deleting them.
         NextCmp->setDeleted();
         NextBr->setDeleted();
         Context.advanceNext();
         Context.advanceNext();
         return true;
       }
     }
   }
   return false;
@@ skipping 110 matching lines @@
   //   mov     <reg>, eax
   //   op      <reg>, [desired_adj]
   //   lock cmpxchg [ptr], <reg>
   //   jne     .LABEL
   //   mov     <dest>, eax
   //
   // If Op_{Lo,Hi} are nullptr, then just copy the value.
   Val = legalize(Val);
   Type Ty = Val->getType();
   if (Ty == IceType_i64) {
-    Variable *T_edx = makeReg(IceType_i32, RegX8632::Reg_edx);
-    Variable *T_eax = makeReg(IceType_i32, RegX8632::Reg_eax);
+    Variable *T_edx = makeReg(IceType_i32, Traits::RegisterSet::Reg_edx);
+    Variable *T_eax = makeReg(IceType_i32, Traits::RegisterSet::Reg_eax);
     OperandX8632Mem *Addr = formMemoryOperand(Ptr, Ty);
     _mov(T_eax, loOperand(Addr));
     _mov(T_edx, hiOperand(Addr));
-    Variable *T_ecx = makeReg(IceType_i32, RegX8632::Reg_ecx);
-    Variable *T_ebx = makeReg(IceType_i32, RegX8632::Reg_ebx);
+    Variable *T_ecx = makeReg(IceType_i32, Traits::RegisterSet::Reg_ecx);
+    Variable *T_ebx = makeReg(IceType_i32, Traits::RegisterSet::Reg_ebx);
     InstX8632Label *Label = InstX8632Label::create(Func, this);
     const bool IsXchg8b = Op_Lo == nullptr && Op_Hi == nullptr;
     if (!IsXchg8b) {
       Context.insert(Label);
       _mov(T_ebx, T_eax);
       (this->*Op_Lo)(T_ebx, loOperand(Val));
       _mov(T_ecx, T_edx);
       (this->*Op_Hi)(T_ecx, hiOperand(Val));
     } else {
       // This is for xchg, which doesn't need an actual Op_Lo/Op_Hi.
       // It just needs the Val loaded into ebx and ecx.
       // That can also be done before the loop.
       _mov(T_ebx, loOperand(Val));
       _mov(T_ecx, hiOperand(Val));
       Context.insert(Label);
     }
     const bool Locked = true;
     _cmpxchg8b(Addr, T_edx, T_eax, T_ecx, T_ebx, Locked);
-    _br(CondX86::Br_ne, Label);
+    _br(Traits::Cond::Br_ne, Label);
     if (!IsXchg8b) {
       // If Val is a variable, model the extended live range of Val through
       // the end of the loop, since it will be re-used by the loop.
       if (Variable *ValVar = llvm::dyn_cast<Variable>(Val)) {
         Variable *ValLo = llvm::cast<Variable>(loOperand(ValVar));
         Variable *ValHi = llvm::cast<Variable>(hiOperand(ValVar));
         Context.insert(InstFakeUse::create(Func, ValLo));
         Context.insert(InstFakeUse::create(Func, ValHi));
       }
     } else {
       // For xchg, the loop is slightly smaller and ebx/ecx are used.
       Context.insert(InstFakeUse::create(Func, T_ebx));
       Context.insert(InstFakeUse::create(Func, T_ecx));
     }
     // The address base (if any) is also reused in the loop.
     if (Variable *Base = Addr->getBase())
       Context.insert(InstFakeUse::create(Func, Base));
     Variable *DestLo = llvm::cast<Variable>(loOperand(Dest));
     Variable *DestHi = llvm::cast<Variable>(hiOperand(Dest));
     _mov(DestLo, T_eax);
     _mov(DestHi, T_edx);
     return;
   }
   OperandX8632Mem *Addr = formMemoryOperand(Ptr, Ty);
-  Variable *T_eax = makeReg(Ty, RegX8632::Reg_eax);
+  Variable *T_eax = makeReg(Ty, Traits::RegisterSet::Reg_eax);
   _mov(T_eax, Addr);
   InstX8632Label *Label = InstX8632Label::create(Func, this);
   Context.insert(Label);
   // We want to pick a different register for T than Eax, so don't use
   // _mov(T == nullptr, T_eax).
   Variable *T = makeReg(Ty);
   _mov(T, T_eax);
   (this->*Op_Lo)(T, Val);
   const bool Locked = true;
   _cmpxchg(Addr, T_eax, T, Locked);
-  _br(CondX86::Br_ne, Label);
+  _br(Traits::Cond::Br_ne, Label);
   // If Val is a variable, model the extended live range of Val through
   // the end of the loop, since it will be re-used by the loop.
   if (Variable *ValVar = llvm::dyn_cast<Variable>(Val)) {
     Context.insert(InstFakeUse::create(Func, ValVar));
   }
   // The address base (if any) is also reused in the loop.
   if (Variable *Base = Addr->getBase())
     Context.insert(InstFakeUse::create(Func, Base));
   _mov(Dest, T_eax);
 }
@@ skipping 43 matching lines @@
   }
   Variable *T_Dest = makeReg(IceType_i32);
   Constant *ThirtyTwo = Ctx->getConstantInt32(32);
   Constant *ThirtyOne = Ctx->getConstantInt32(31);
   if (Cttz) {
     _mov(T_Dest, ThirtyTwo);
   } else {
     Constant *SixtyThree = Ctx->getConstantInt32(63);
     _mov(T_Dest, SixtyThree);
   }
-  _cmov(T_Dest, T, CondX86::Br_ne);
+  _cmov(T_Dest, T, Traits::Cond::Br_ne);
   if (!Cttz) {
     _xor(T_Dest, ThirtyOne);
   }
   if (Ty == IceType_i32) {
     _mov(Dest, T_Dest);
     return;
   }
   _add(T_Dest, ThirtyTwo);
   Variable *DestLo = llvm::cast<Variable>(loOperand(Dest));
   Variable *DestHi = llvm::cast<Variable>(hiOperand(Dest));
   // Will be using "test" on this, so we need a registerized variable.
   Variable *SecondVar = legalizeToVar(SecondVal);
   Variable *T_Dest2 = makeReg(IceType_i32);
   if (Cttz) {
     _bsf(T_Dest2, SecondVar);
   } else {
     _bsr(T_Dest2, SecondVar);
     _xor(T_Dest2, ThirtyOne);
   }
   _test(SecondVar, SecondVar);
-  _cmov(T_Dest2, T_Dest, CondX86::Br_e);
+  _cmov(T_Dest2, T_Dest, Traits::Cond::Br_e);
   _mov(DestLo, T_Dest2);
   _mov(DestHi, Ctx->getConstantZero(IceType_i32));
 }
 
 bool isAdd(const Inst *Inst) {
   if (const InstArithmetic *Arith =
           llvm::dyn_cast_or_null<const InstArithmetic>(Inst)) {
     return (Arith->getOp() == InstArithmetic::Add);
   }
   return false;
@@ skipping 281 matching lines @@
 void TargetX86Base<Machine>::lowerPhi(const InstPhi * /*Inst*/) {
   Func->setError("Phi found in regular instruction list");
 }
 
 template <class Machine>
 void TargetX86Base<Machine>::lowerRet(const InstRet *Inst) {
   Variable *Reg = nullptr;
   if (Inst->hasRetValue()) {
     Operand *Src0 = legalize(Inst->getRetValue());
     if (Src0->getType() == IceType_i64) {
-      Variable *eax = legalizeToVar(loOperand(Src0), RegX8632::Reg_eax);
-      Variable *edx = legalizeToVar(hiOperand(Src0), RegX8632::Reg_edx);
+      Variable *eax =
+          legalizeToVar(loOperand(Src0), Traits::RegisterSet::Reg_eax);
+      Variable *edx =
+          legalizeToVar(hiOperand(Src0), Traits::RegisterSet::Reg_edx);
       Reg = eax;
       Context.insert(InstFakeUse::create(Func, edx));
     } else if (isScalarFloatingType(Src0->getType())) {
       _fld(Src0);
     } else if (isVectorType(Src0->getType())) {
-      Reg = legalizeToVar(Src0, RegX8632::Reg_xmm0);
+      Reg = legalizeToVar(Src0, Traits::RegisterSet::Reg_xmm0);
     } else {
-      _mov(Reg, Src0, RegX8632::Reg_eax);
+      _mov(Reg, Src0, Traits::RegisterSet::Reg_eax);
     }
   }
   // Add a ret instruction even if sandboxing is enabled, because
   // addEpilog explicitly looks for a ret instruction as a marker for
   // where to insert the frame removal instructions.
   _ret(Reg);
   // Add a fake use of esp to make sure esp stays alive for the entire
   // function.  Otherwise post-call esp adjustments get dead-code
   // eliminated.  TODO: Are there more places where the fake use
   // should be inserted?  E.g. "void f(int n){while(1) g(n);}" may not
   // have a ret instruction.
-  Variable *esp = Func->getTarget()->getPhysicalRegister(RegX8632::Reg_esp);
+  Variable *esp =
+      Func->getTarget()->getPhysicalRegister(Traits::RegisterSet::Reg_esp);
   Context.insert(InstFakeUse::create(Func, esp));
 }
 
 template <class Machine>
 void TargetX86Base<Machine>::lowerSelect(const InstSelect *Inst) {
   Variable *Dest = Inst->getDest();
   Type DestTy = Dest->getType();
   Operand *SrcT = Inst->getTrueOperand();
   Operand *SrcF = Inst->getFalseOperand();
   Operand *Condition = Inst->getCondition();
 
   if (isVectorType(DestTy)) {
     Type SrcTy = SrcT->getType();
     Variable *T = makeReg(SrcTy);
     Operand *SrcTRM = legalize(SrcT, Legal_Reg | Legal_Mem);
     Operand *SrcFRM = legalize(SrcF, Legal_Reg | Legal_Mem);
-    if (InstructionSet >= Machine::SSE4_1) {
+    if (InstructionSet >= Traits::SSE4_1) {
       // TODO(wala): If the condition operand is a constant, use blendps
       // or pblendw.
       //
       // Use blendvps or pblendvb to implement select.
       if (SrcTy == IceType_v4i1 || SrcTy == IceType_v4i32 ||
           SrcTy == IceType_v4f32) {
         Operand *ConditionRM = legalize(Condition, Legal_Reg | Legal_Mem);
-        Variable *xmm0 = makeReg(IceType_v4i32, RegX8632::Reg_xmm0);
+        Variable *xmm0 = makeReg(IceType_v4i32, Traits::RegisterSet::Reg_xmm0);
         _movp(xmm0, ConditionRM);
         _psll(xmm0, Ctx->getConstantInt8(31));
         _movp(T, SrcFRM);
         _blendvps(T, SrcTRM, xmm0);
         _movp(Dest, T);
       } else {
         assert(typeNumElements(SrcTy) == 8 || typeNumElements(SrcTy) == 16);
         Type SignExtTy = Condition->getType() == IceType_v8i1 ? IceType_v8i16
                                                               : IceType_v16i8;
-        Variable *xmm0 = makeReg(SignExtTy, RegX8632::Reg_xmm0);
+        Variable *xmm0 = makeReg(SignExtTy, Traits::RegisterSet::Reg_xmm0);
         lowerCast(InstCast::create(Func, InstCast::Sext, xmm0, Condition));
         _movp(T, SrcFRM);
         _pblendvb(T, SrcTRM, xmm0);
         _movp(Dest, T);
       }
       return;
     }
-    // Lower select without Machine::SSE4.1:
+    // Lower select without Traits::SSE4.1:
     // a=d?b:c ==>
     //   if elementtype(d) != i1:
     //      d=sext(d);
     //   a=(b&d)|(c&~d);
     Variable *T2 = makeReg(SrcTy);
     // Sign extend the condition operand if applicable.
     if (SrcTy == IceType_v4f32) {
       // The sext operation takes only integer arguments.
       Variable *T3 = Func->template makeVariable(IceType_v4i32);
       lowerCast(InstCast::create(Func, InstCast::Sext, T3, Condition));
       _movp(T, T3);
     } else if (typeElementType(SrcTy) != IceType_i1) {
       lowerCast(InstCast::create(Func, InstCast::Sext, T, Condition));
     } else {
       Operand *ConditionRM = legalize(Condition, Legal_Reg | Legal_Mem);
       _movp(T, ConditionRM);
     }
     _movp(T2, T);
     _pand(T, SrcTRM);
     _pandn(T2, SrcFRM);
     _por(T, T2);
     _movp(Dest, T);
 
     return;
   }
 
-  CondX86::BrCond Cond = CondX86::Br_ne;
+  typename Traits::Cond::BrCond Cond = Traits::Cond::Br_ne;
   Operand *CmpOpnd0 = nullptr;
   Operand *CmpOpnd1 = nullptr;
   // Handle folding opportunities.
   if (const class Inst *Producer = FoldingInfo.getProducerFor(Condition)) {
     assert(Producer->isDeleted());
     switch (BoolFolding::getProducerKind(Producer)) {
     default:
       break;
     case BoolFolding::PK_Icmp32: {
       auto *Cmp = llvm::dyn_cast<InstIcmp>(Producer);
@@ skipping 124 matching lines @@
       Src0Hi = legalizeToVar(Src0Hi);
     } else {
       Src0Lo = legalize(Src0Lo, Legal_Reg | Legal_Mem);
       Src0Hi = legalize(Src0Hi, Legal_Reg | Legal_Mem);
     }
     for (SizeT I = 0; I < NumCases; ++I) {
       Constant *ValueLo = Ctx->getConstantInt32(Inst->getValue(I));
       Constant *ValueHi = Ctx->getConstantInt32(Inst->getValue(I) >> 32);
       InstX8632Label *Label = InstX8632Label::create(Func, this);
       _cmp(Src0Lo, ValueLo);
-      _br(CondX86::Br_ne, Label);
+      _br(Traits::Cond::Br_ne, Label);
       _cmp(Src0Hi, ValueHi);
-      _br(CondX86::Br_e, Inst->getLabel(I));
+      _br(Traits::Cond::Br_e, Inst->getLabel(I));
       Context.insert(Label);
     }
     _br(Inst->getLabelDefault());
     return;
   }
   // OK, we'll be slightly less naive by forcing Src into a physical
   // register if there are 2 or more uses.
   if (NumCases >= 2)
     Src0 = legalizeToVar(Src0);
   else
     Src0 = legalize(Src0, Legal_Reg | Legal_Mem);
   for (SizeT I = 0; I < NumCases; ++I) {
     Constant *Value = Ctx->getConstantInt32(Inst->getValue(I));
     _cmp(Src0, Value);
-    _br(CondX86::Br_e, Inst->getLabel(I));
+    _br(Traits::Cond::Br_e, Inst->getLabel(I));
   }
 
   _br(Inst->getLabelDefault());
 }
 
 template <class Machine>
 void TargetX86Base<Machine>::scalarizeArithmetic(InstArithmetic::OpKind Kind,
                                                  Variable *Dest, Operand *Src0,
                                                  Operand *Src1) {
   assert(isVectorType(Dest->getType()));
@@ skipping 628 matching lines @@
     return;
   inferTwoAddress();
 }
 
 template <class Machine>
 void TargetX86Base<Machine>::makeRandomRegisterPermutation(
     llvm::SmallVectorImpl<int32_t> &Permutation,
     const llvm::SmallBitVector &ExcludeRegisters) const {
   // TODO(stichnot): Declaring Permutation this way loses type/size
   // information.  Fix this in conjunction with the caller-side TODO.
-  assert(Permutation.size() >= RegX8632::Reg_NUM);
+  assert(Permutation.size() >= Traits::RegisterSet::Reg_NUM);
   // Expected upper bound on the number of registers in a single
   // equivalence class.  For x86-32, this would comprise the 8 XMM
   // registers.  This is for performance, not correctness.
   static const unsigned MaxEquivalenceClassSize = 8;
   typedef llvm::SmallVector<int32_t, MaxEquivalenceClassSize> RegisterList;
   typedef std::map<uint32_t, RegisterList> EquivalenceClassMap;
   EquivalenceClassMap EquivalenceClasses;
   SizeT NumShuffled = 0, NumPreserved = 0;
 
 // Build up the equivalence classes of registers by looking at the
 // register properties as well as whether the registers should be
 // explicitly excluded from shuffling.
 #define X(val, encode, name, name16, name8, scratch, preserved, stackptr,      \
           frameptr, isI8, isInt, isFP)                                         \
-  if (ExcludeRegisters[RegX8632::val]) {                                       \
+  if (ExcludeRegisters[Traits::RegisterSet::val]) {                            \
     /* val stays the same in the resulting permutation. */                     \
-    Permutation[RegX8632::val] = RegX8632::val;                                \
+    Permutation[Traits::RegisterSet::val] = Traits::RegisterSet::val;          \
     ++NumPreserved;                                                            \
   } else {                                                                     \
     const uint32_t Index = (scratch << 0) | (preserved << 1) | (isI8 << 2) |   \
                            (isInt << 3) | (isFP << 4);                         \
     /* val is assigned to an equivalence class based on its properties. */     \
-    EquivalenceClasses[Index].push_back(RegX8632::val);                        \
+    EquivalenceClasses[Index].push_back(Traits::RegisterSet::val);             \
   }
   REGX8632_TABLE
 #undef X
 
   RandomNumberGeneratorWrapper RNG(Ctx->getRNG());
 
   // Shuffle the resulting equivalence classes.
   for (auto I : EquivalenceClasses) {
     const RegisterList &List = I.second;
     RegisterList Shuffled(List);
     RandomShuffle(Shuffled.begin(), Shuffled.end(), RNG);
     for (size_t SI = 0, SE = Shuffled.size(); SI < SE; ++SI) {
       Permutation[List[SI]] = Shuffled[SI];
       ++NumShuffled;
     }
   }
 
-  assert(NumShuffled + NumPreserved == RegX8632::Reg_NUM);
+  assert(NumShuffled + NumPreserved == Traits::RegisterSet::Reg_NUM);
 
   if (Func->isVerbose(IceV_Random)) {
     OstreamLocker L(Func->getContext());
     Ostream &Str = Func->getContext()->getStrDump();
     Str << "Register equivalence classes:\n";
     for (auto I : EquivalenceClasses) {
       Str << "{";
       const RegisterList &List = I.second;
       bool First = true;
       for (int32_t Register : List) {
@@ skipping 233 matching lines @@
   }
   // the offset is not eligible for blinding or pooling, return the original
   // mem operand
   return MemOperand;
 }
 
 } // end of namespace X86Internal
 } // end of namespace Ice
 
 #endif // SUBZERO_SRC_ICETARGETLOWERINGX86BASEIMPL_H