Move X8632-specific Assembler stuff to Machine Traits.

src/IceTargetLoweringX86Base.h

 //===- subzero/src/IceTargetLoweringX86Base.h - x86 lowering ----*- C++ -*-===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file declares the TargetLoweringX86 template class, which
@@ skipping 89 matching lines @@
   using Machine::regAlloc;
   using Machine::resetStackAdjustment;
 
   static TargetX86Base *create(Cfg *Func) { return new TargetX86Base(Func); }
 
   void translateOm1() override;
   void translateO2() override;
   void doLoadOpt();
   bool doBranchOpt(Inst *I, const CfgNode *NextNode) override;
 
-  SizeT getNumRegisters() const override { return RegX8632::Reg_NUM; }
+  SizeT getNumRegisters() const override {
+    return Traits::RegisterSet::Reg_NUM;
+  }
   Variable *getPhysicalRegister(SizeT RegNum, Type Ty = IceType_void) override;
   IceString getRegName(SizeT RegNum, Type Ty) const override;
   llvm::SmallBitVector getRegisterSet(RegSetMask Include,
                                       RegSetMask Exclude) const override;
   const llvm::SmallBitVector &getRegisterSetForType(Type Ty) const override {
     return TypeToRegisterSet[Ty];
   }
   bool hasFramePointer() const override { return IsEbpBasedFrame; }
   SizeT getFrameOrStackReg() const override {
-    return IsEbpBasedFrame ? RegX8632::Reg_ebp : RegX8632::Reg_esp;
+    return IsEbpBasedFrame ? Traits::RegisterSet::Reg_ebp
+                           : Traits::RegisterSet::Reg_esp;
   }
   size_t typeWidthInBytesOnStack(Type Ty) const override {
     // Round up to the next multiple of 4 bytes.  In particular, i1,
     // i8, and i16 are rounded up to 4 bytes.
     return (typeWidthInBytes(Ty) + 3) & ~3;
   }
 
   void emitVariable(const Variable *Var) const override;
 
   const char *getConstantPrefix() const final { return "$"; }
@@ skipping 10 matching lines @@
   // Ensure that a 64-bit Variable has been split into 2 32-bit
   // Variables, creating them if necessary.  This is needed for all
   // I64 operations, and it is needed for pushing F64 arguments for
   // function calls using the 32-bit push instruction (though the
   // latter could be done by directly writing to the stack).
   void split64(Variable *Var);
   Operand *loOperand(Operand *Operand);
   Operand *hiOperand(Operand *Operand);
   void finishArgumentLowering(Variable *Arg, Variable *FramePtr,
                               size_t BasicFrameOffset, size_t &InArgsSizeBytes);
-  X8632::Address stackVarToAsmOperand(const Variable *Var) const final;
+  typename Traits::Address
+  stackVarToAsmOperand(const Variable *Var) const final;
 
   typename Traits::InstructionSet getInstructionSet() const final {
     return InstructionSet;
   }
 
 protected:
   explicit TargetX86Base(Cfg *Func);
 
   void postLower() override;
 
@@ skipping 86 matching lines @@
                                  int32_t RegNum = Variable::NoRegister);
 
   // Return a memory operand corresponding to a stack allocated Variable.
   OperandX8632Mem *getMemoryOperandForStackSlot(Type Ty, Variable *Slot,
                                                 uint32_t Offset = 0);
 
   void makeRandomRegisterPermutation(
       llvm::SmallVectorImpl<int32_t> &Permutation,
       const llvm::SmallBitVector &ExcludeRegisters) const override;
 
+  // TODO(jpp): move the helper methods below to the MachineTraits.

[jvoung (off chromium), 2015/06/30 21:19:48]

So the idea is that this file shouldn't say, for instance, InstX8632XYZ or?

[John, 2015/06/30 21:42:00]

Yes, that's correct. My plan is to have something like

template <class Type, class... Args> Type* createInst(Args&&... args) {
  return TraitsMagic<Type>::create(std::forward<Args>(args)...);
}

so that we can isolate common x86 stuff (add, sub, sbb, etc) from x8632
(cmpxchg8b, fld, fstp, etc).

   // The following are helpers that insert lowered x86 instructions
   // with minimal syntactic overhead, so that the lowering code can
   // look as close to assembly as practical.
   void _adc(Variable *Dest, Operand *Src0) {
     Context.insert(InstX8632Adc::create(Func, Dest, Src0));
   }
   void _adc_rmw(OperandX8632Mem *DestSrc0, Operand *Src1) {
     Context.insert(InstX8632AdcRMW::create(Func, DestSrc0, Src1));
   }
   void _add(Variable *Dest, Operand *Src0) {
     Context.insert(InstX8632Add::create(Func, Dest, Src0));
   }
   void _add_rmw(OperandX8632Mem *DestSrc0, Operand *Src1) {
     Context.insert(InstX8632AddRMW::create(Func, DestSrc0, Src1));
   }
   void _adjust_stack(int32_t Amount) {
     Context.insert(InstX8632AdjustStack::create(
-        Func, Amount, getPhysicalRegister(RegX8632::Reg_esp)));
+        Func, Amount, getPhysicalRegister(Traits::RegisterSet::Reg_esp)));
   }
   void _addps(Variable *Dest, Operand *Src0) {
     Context.insert(InstX8632Addps::create(Func, Dest, Src0));
   }
   void _addss(Variable *Dest, Operand *Src0) {
     Context.insert(InstX8632Addss::create(Func, Dest, Src0));
   }
   void _and(Variable *Dest, Operand *Src0) {
     Context.insert(InstX8632And::create(Func, Dest, Src0));
   }
   void _and_rmw(OperandX8632Mem *DestSrc0, Operand *Src1) {
     Context.insert(InstX8632AndRMW::create(Func, DestSrc0, Src1));
   }
   void _blendvps(Variable *Dest, Operand *Src0, Operand *Src1) {
     Context.insert(InstX8632Blendvps::create(Func, Dest, Src0, Src1));
   }
-  void _br(CondX86::BrCond Condition, CfgNode *TargetTrue,
+  void _br(typename Traits::Cond::BrCond Condition, CfgNode *TargetTrue,
            CfgNode *TargetFalse) {
     Context.insert(
         InstX8632Br::create(Func, TargetTrue, TargetFalse, Condition));
   }
   void _br(CfgNode *Target) {
     Context.insert(InstX8632Br::create(Func, Target));
   }
-  void _br(CondX86::BrCond Condition, CfgNode *Target) {
+  void _br(typename Traits::Cond::BrCond Condition, CfgNode *Target) {
     Context.insert(InstX8632Br::create(Func, Target, Condition));
   }
-  void _br(CondX86::BrCond Condition, InstX8632Label *Label) {
+  void _br(typename Traits::Cond::BrCond Condition, InstX8632Label *Label) {
     Context.insert(InstX8632Br::create(Func, Label, Condition));
   }
   void _bsf(Variable *Dest, Operand *Src0) {
     Context.insert(InstX8632Bsf::create(Func, Dest, Src0));
   }
   void _bsr(Variable *Dest, Operand *Src0) {
     Context.insert(InstX8632Bsr::create(Func, Dest, Src0));
   }
   void _bswap(Variable *SrcDest) {
     Context.insert(InstX8632Bswap::create(Func, SrcDest));
   }
   void _cbwdq(Variable *Dest, Operand *Src0) {
     Context.insert(InstX8632Cbwdq::create(Func, Dest, Src0));
   }
-  void _cmov(Variable *Dest, Operand *Src0, CondX86::BrCond Condition) {
+  void _cmov(Variable *Dest, Operand *Src0,
+             typename Traits::Cond::BrCond Condition) {
     Context.insert(InstX8632Cmov::create(Func, Dest, Src0, Condition));
   }
   void _cmp(Operand *Src0, Operand *Src1) {
     Context.insert(InstX8632Icmp::create(Func, Src0, Src1));
   }
-  void _cmpps(Variable *Dest, Operand *Src0, CondX86::CmppsCond Condition) {
+  void _cmpps(Variable *Dest, Operand *Src0,
+              typename Traits::Cond::CmppsCond Condition) {
     Context.insert(InstX8632Cmpps::create(Func, Dest, Src0, Condition));
   }
   void _cmpxchg(Operand *DestOrAddr, Variable *Eax, Variable *Desired,
                 bool Locked) {
     Context.insert(
         InstX8632Cmpxchg::create(Func, DestOrAddr, Eax, Desired, Locked));
     // Mark eax as possibly modified by cmpxchg.
     Context.insert(
         InstFakeDef::create(Func, Eax, llvm::dyn_cast<Variable>(DestOrAddr)));
     _set_dest_nonkillable();
@@ skipping 161 matching lines @@
   }
   void _sar(Variable *Dest, Operand *Src0) {
     Context.insert(InstX8632Sar::create(Func, Dest, Src0));
   }
   void _sbb(Variable *Dest, Operand *Src0) {
     Context.insert(InstX8632Sbb::create(Func, Dest, Src0));
   }
   void _sbb_rmw(OperandX8632Mem *DestSrc0, Operand *Src1) {
     Context.insert(InstX8632SbbRMW::create(Func, DestSrc0, Src1));
   }
-  void _setcc(Variable *Dest, CondX86::BrCond Condition) {
+  void _setcc(Variable *Dest, typename Traits::Cond::BrCond Condition) {
     Context.insert(InstX8632Setcc::create(Func, Dest, Condition));
   }
   void _shl(Variable *Dest, Operand *Src0) {
     Context.insert(InstX8632Shl::create(Func, Dest, Src0));
   }
   void _shld(Variable *Dest, Variable *Src0, Variable *Src1) {
     Context.insert(InstX8632Shld::create(Func, Dest, Src0, Src1));
   }
   void _shr(Variable *Dest, Operand *Src0) {
     Context.insert(InstX8632Shr::create(Func, Dest, Src0));
@@ skipping 88 matching lines @@
 private:
   ~TargetX86Base() override {}
   BoolFolding FoldingInfo;
 };
 } // end of namespace X86Internal
 } // end of namespace Ice
 
 #include "IceTargetLoweringX86BaseImpl.h"
 
 #endif // SUBZERO_SRC_ICETARGETLOWERINGX86BASE_H