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| 1 //===- subzero/src/IceRegistersX8632.h - Register information ---*- C++ -*-===// | 1 //===- subzero/src/IceRegistersX8632.h - Register information ---*- C++ -*-===// |
| 2 // | 2 // |
| 3 // The Subzero Code Generator | 3 // The Subzero Code Generator |
| 4 // | 4 // |
| 5 // This file is distributed under the University of Illinois Open Source | 5 // This file is distributed under the University of Illinois Open Source |
| 6 // License. See LICENSE.TXT for details. | 6 // License. See LICENSE.TXT for details. |
| 7 // | 7 // |
| 8 //===----------------------------------------------------------------------===// | 8 //===----------------------------------------------------------------------===// |
| 9 // | 9 // |
| 10 // This file declares the registers and their encodings for x86-32. | 10 // This file declares the registers and their encodings for x86-32. |
| 11 // | 11 // |
| 12 //===----------------------------------------------------------------------===// | 12 //===----------------------------------------------------------------------===// |
| 13 | 13 |
| 14 #ifndef SUBZERO_SRC_ICEREGISTERSX8632_H | 14 #ifndef SUBZERO_SRC_ICEREGISTERSX8632_H |
| 15 #define SUBZERO_SRC_ICEREGISTERSX8632_H | 15 #define SUBZERO_SRC_ICEREGISTERSX8632_H |
| 16 | 16 |
| 17 #include "IceDefs.h" | 17 #include "IceDefs.h" |
| 18 #include "IceInstX8632.def" | 18 #include "IceInstX8632.def" |
| 19 #include "IceTypes.h" | 19 #include "IceTypes.h" |
| 20 | 20 |
| 21 namespace Ice { | 21 namespace Ice { |
| 22 | 22 |
| 23 namespace RegX8632 { | 23 class RegX8632 { |
|
jvoung (off chromium)
2015/06/30 21:19:48
Should RegX8664 get the same treatment (namespace
John
2015/06/30 21:42:00
This is already part of this patch. Nice catch, th
jvoung (off chromium)
2015/06/30 22:26:46
I see "ConditionCodesX8664.h", but not RegistersX8
John
2015/06/30 22:29:29
I got confused.... Good catch.
| |
| 24 | 24 public: |
| 25 // An enum of every register. The enum value may not match the encoding | 25 // An enum of every register. The enum value may not match the encoding |
| 26 // used to binary encode register operands in instructions. | 26 // used to binary encode register operands in instructions. |
| 27 enum AllRegisters { | 27 enum AllRegisters { |
| 28 #define X(val, encode, name, name16, name8, scratch, preserved, stackptr, \ | 28 #define X(val, encode, name, name16, name8, scratch, preserved, stackptr, \ |
| 29 frameptr, isI8, isInt, isFP) \ | 29 frameptr, isI8, isInt, isFP) \ |
| 30 val, | 30 val, |
| 31 REGX8632_TABLE | 31 REGX8632_TABLE |
| 32 #undef X | 32 #undef X |
| 33 Reg_NUM, | 33 Reg_NUM, |
| 34 #define X(val, init) val init, | 34 #define X(val, init) val init, |
| 35 REGX8632_TABLE_BOUNDS | 35 REGX8632_TABLE_BOUNDS |
| 36 #undef X | 36 #undef X |
| 37 }; | 37 }; |
| 38 | 38 |
| 39 // An enum of GPR Registers. The enum value does match the encoding used | 39 // An enum of GPR Registers. The enum value does match the encoding used |
| 40 // to binary encode register operands in instructions. | 40 // to binary encode register operands in instructions. |
| 41 enum GPRRegister { | 41 enum GPRRegister { |
| 42 #define X(val, encode, name, name16, name8, scratch, preserved, stackptr, \ | 42 #define X(val, encode, name, name16, name8, scratch, preserved, stackptr, \ |
| 43 frameptr, isI8, isInt, isFP) \ | 43 frameptr, isI8, isInt, isFP) \ |
| 44 Encoded_##val encode, | 44 Encoded_##val encode, |
| 45 REGX8632_GPR_TABLE | 45 REGX8632_GPR_TABLE |
| 46 #undef X | 46 #undef X |
| 47 Encoded_Not_GPR = -1 | 47 Encoded_Not_GPR = -1 |
| 48 }; | 48 }; |
| 49 | 49 |
| 50 // An enum of XMM Registers. The enum value does match the encoding used | 50 // An enum of XMM Registers. The enum value does match the encoding used |
| 51 // to binary encode register operands in instructions. | 51 // to binary encode register operands in instructions. |
| 52 enum XmmRegister { | 52 enum XmmRegister { |
| 53 #define X(val, encode, name, name16, name8, scratch, preserved, stackptr, \ | 53 #define X(val, encode, name, name16, name8, scratch, preserved, stackptr, \ |
| 54 frameptr, isI8, isInt, isFP) \ | 54 frameptr, isI8, isInt, isFP) \ |
| 55 Encoded_##val encode, | 55 Encoded_##val encode, |
| 56 REGX8632_XMM_TABLE | 56 REGX8632_XMM_TABLE |
| 57 #undef X | 57 #undef X |
| 58 Encoded_Not_Xmm = -1 | 58 Encoded_Not_Xmm = -1 |
| 59 }; | |
| 60 | |
| 61 // An enum of Byte Registers. The enum value does match the encoding used | |
| 62 // to binary encode register operands in instructions. | |
| 63 enum ByteRegister { | |
| 64 #define X(val, encode) Encoded_##val encode, | |
| 65 REGX8632_BYTEREG_TABLE | |
| 66 #undef X | |
| 67 Encoded_Not_ByteReg = -1 | |
| 68 }; | |
| 69 | |
| 70 // An enum of X87 Stack Registers. The enum value does match the encoding used | |
| 71 // to binary encode register operands in instructions. | |
| 72 enum X87STRegister { | |
| 73 #define X(val, encode, name) Encoded_##val encode, | |
| 74 X87ST_REGX8632_TABLE | |
| 75 #undef X | |
| 76 Encoded_Not_X87STReg = -1 | |
| 77 }; | |
| 78 | |
| 79 static inline GPRRegister getEncodedGPR(int32_t RegNum) { | |
| 80 assert(Reg_GPR_First <= RegNum && RegNum <= Reg_GPR_Last); | |
| 81 return GPRRegister(RegNum - Reg_GPR_First); | |
| 82 } | |
| 83 | |
| 84 static inline XmmRegister getEncodedXmm(int32_t RegNum) { | |
| 85 assert(Reg_XMM_First <= RegNum && RegNum <= Reg_XMM_Last); | |
| 86 return XmmRegister(RegNum - Reg_XMM_First); | |
| 87 } | |
| 88 | |
| 89 static inline ByteRegister getEncodedByteReg(int32_t RegNum) { | |
| 90 assert(RegNum == Reg_ah || (Reg_GPR_First <= RegNum && RegNum <= Reg_ebx)); | |
| 91 if (RegNum == Reg_ah) | |
| 92 return Encoded_Reg_ah; | |
| 93 return ByteRegister(RegNum - Reg_GPR_First); | |
| 94 } | |
| 95 | |
| 96 static inline GPRRegister getEncodedByteRegOrGPR(Type Ty, int32_t RegNum) { | |
| 97 if (isByteSizedType(Ty)) | |
| 98 return GPRRegister(getEncodedByteReg(RegNum)); | |
| 99 else | |
| 100 return getEncodedGPR(RegNum); | |
| 101 } | |
| 102 | |
| 103 static inline X87STRegister getEncodedSTReg(int32_t RegNum) { | |
| 104 assert(Encoded_X87ST_First <= RegNum && RegNum <= Encoded_X87ST_Last); | |
| 105 return X87STRegister(RegNum); | |
| 106 } | |
| 59 }; | 107 }; |
| 60 | 108 |
| 61 // An enum of Byte Registers. The enum value does match the encoding used | |
| 62 // to binary encode register operands in instructions. | |
| 63 enum ByteRegister { | |
| 64 #define X(val, encode) Encoded_##val encode, | |
| 65 REGX8632_BYTEREG_TABLE | |
| 66 #undef X | |
| 67 Encoded_Not_ByteReg = -1 | |
| 68 }; | |
| 69 | |
| 70 // An enum of X87 Stack Registers. The enum value does match the encoding used | |
| 71 // to binary encode register operands in instructions. | |
| 72 enum X87STRegister { | |
| 73 #define X(val, encode, name) Encoded_##val encode, | |
| 74 X87ST_REGX8632_TABLE | |
| 75 #undef X | |
| 76 Encoded_Not_X87STReg = -1 | |
| 77 }; | |
| 78 | |
| 79 static inline GPRRegister getEncodedGPR(int32_t RegNum) { | |
| 80 assert(Reg_GPR_First <= RegNum && RegNum <= Reg_GPR_Last); | |
| 81 return GPRRegister(RegNum - Reg_GPR_First); | |
| 82 } | |
| 83 | |
| 84 static inline XmmRegister getEncodedXmm(int32_t RegNum) { | |
| 85 assert(Reg_XMM_First <= RegNum && RegNum <= Reg_XMM_Last); | |
| 86 return XmmRegister(RegNum - Reg_XMM_First); | |
| 87 } | |
| 88 | |
| 89 static inline ByteRegister getEncodedByteReg(int32_t RegNum) { | |
| 90 assert(RegNum == Reg_ah || (Reg_GPR_First <= RegNum && RegNum <= Reg_ebx)); | |
| 91 if (RegNum == Reg_ah) | |
| 92 return Encoded_Reg_ah; | |
| 93 return ByteRegister(RegNum - Reg_GPR_First); | |
| 94 } | |
| 95 | |
| 96 static inline GPRRegister getEncodedByteRegOrGPR(Type Ty, int32_t RegNum) { | |
| 97 if (isByteSizedType(Ty)) | |
| 98 return GPRRegister(getEncodedByteReg(RegNum)); | |
| 99 else | |
| 100 return getEncodedGPR(RegNum); | |
| 101 } | |
| 102 | |
| 103 static inline X87STRegister getEncodedSTReg(int32_t RegNum) { | |
| 104 assert(Encoded_X87ST_First <= RegNum && RegNum <= Encoded_X87ST_Last); | |
| 105 return X87STRegister(RegNum); | |
| 106 } | |
| 107 | |
| 108 } // end of namespace RegX8632 | |
| 109 | |
| 110 } // end of namespace Ice | 109 } // end of namespace Ice |
| 111 | 110 |
| 112 #endif // SUBZERO_SRC_ICEREGISTERSX8632_H | 111 #endif // SUBZERO_SRC_ICEREGISTERSX8632_H |
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