ARM lowering integer divide and remainder, with div by 0 checks.

src/IceInstARM32.h

 //===- subzero/src/IceInstARM32.h - ARM32 machine instructions --*- C++ -*-===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file declares the InstARM32 and OperandARM32 classes and
@@ skipping 244 matching lines @@
     Adc,
     Add,
     Adjuststack,
     And,
     Asr,
     Bic,
     Br,
     Call,
     Cmp,
     Eor,
+    Label,

[jvoung (off chromium), 2015/06/29 21:44:28]

Would it make sense to just make Label part of the high-level Ice?

[Jim Stichnoth, 2015/06/30 14:14:08]

That seems reasonable.

[jvoung (off chromium), 2015/06/30 16:58:07]

Okay will try that in a separate CL.

     Ldr,
     Lsl,
     Lsr,
     Mla,
+    Mls,
     Mov,
     Movt,
     Movw,
     Mul,
     Mvn,
     Orr,
     Pop,
     Push,
     Ret,
     Rsb,
     Sbc,
+    Sdiv,
     Str,
     Sub,
     Sxt,
+    Trap,
+    Tst,
+    Udiv,
     Umull,
     Uxt
   };
 
   static const char *getWidthString(Type Ty);
   static CondARM32::Cond getOppositeCondition(CondARM32::Cond Cond);
 
   void dump(const Cfg *Func) const override;
 
 protected:
@@ skipping 22 matching lines @@
   static const char *predString(CondARM32::Cond Predicate);
   void dumpOpcodePred(Ostream &Str, const char *Opcode, Type Ty) const;
 
   // Shared emit routines for common forms of instructions.
   static void emitUnaryopGPR(const char *Opcode, const InstARM32Pred *Inst,
                              const Cfg *Func);
   static void emitTwoAddr(const char *Opcode, const InstARM32Pred *Inst,
                           const Cfg *Func);
   static void emitThreeAddr(const char *Opcode, const InstARM32Pred *Inst,
                             const Cfg *Func, bool SetFlags);
+  static void emitFourAddr(const char *Opcode, const InstARM32Pred *Inst,
+                           const Cfg *Func);
 
 protected:
   CondARM32::Cond Predicate;
 };
 
 template <typename StreamType>
 inline StreamType &operator<<(StreamType &Stream, CondARM32::Cond Predicate) {
   Stream << InstARM32Pred::predString(Predicate);
   return Stream;
 }
@@ skipping 174 matching lines @@
                         Operand *Src2, CondARM32::Cond Predicate, bool SetFlags)
       : InstARM32Pred(Func, K, 2, Dest, Predicate), SetFlags(SetFlags) {
     addSource(Src1);
     addSource(Src2);
   }
 
   static const char *Opcode;
   bool SetFlags;
 };
 
+// Instructions of the form x := a op1 (y op2 z). E.g., multiply accumulate.
+template <InstARM32::InstKindARM32 K>
+class InstARM32FourAddrGPR : public InstARM32Pred {
+  InstARM32FourAddrGPR() = delete;
+  InstARM32FourAddrGPR(const InstARM32FourAddrGPR &) = delete;
+  InstARM32FourAddrGPR &operator=(const InstARM32FourAddrGPR &) = delete;
+
+public:
+  // Every operand must be a register.
+  static InstARM32FourAddrGPR *create(Cfg *Func, Variable *Dest, Variable *Src1,
+                                      Variable *Src2, Variable *Src3,
+                                      CondARM32::Cond Predicate) {
+    return new (Func->allocate<InstARM32FourAddrGPR>())
+        InstARM32FourAddrGPR(Func, Dest, Src1, Src2, Src3, Predicate);
+  }
+  void emit(const Cfg *Func) const override {
+    if (!BuildDefs::dump())
+      return;
+    emitFourAddr(Opcode, this, Func);
+  }
+  void emitIAS(const Cfg *Func) const override {
+    (void)Func;
+    llvm::report_fatal_error("Not yet implemented");
+  }
+  void dump(const Cfg *Func) const override {
+    if (!BuildDefs::dump())
+      return;
+    Ostream &Str = Func->getContext()->getStrDump();
+    dumpDest(Func);
+    Str << " = ";
+    dumpOpcodePred(Str, Opcode, getDest()->getType());
+    Str << " ";
+    dumpSources(Func);
+  }
+  static bool classof(const Inst *Inst) { return isClassof(Inst, K); }
+
+private:
+  InstARM32FourAddrGPR(Cfg *Func, Variable *Dest, Variable *Src1,
+                       Variable *Src2, Variable *Src3,
+                       CondARM32::Cond Predicate)
+      : InstARM32Pred(Func, K, 3, Dest, Predicate) {
+    addSource(Src1);
+    addSource(Src2);
+    addSource(Src3);
+  }
+
+  static const char *Opcode;
+};
+
 typedef InstARM32ThreeAddrGPR<InstARM32::Adc> InstARM32Adc;
 typedef InstARM32ThreeAddrGPR<InstARM32::Add> InstARM32Add;
 typedef InstARM32ThreeAddrGPR<InstARM32::And> InstARM32And;
 typedef InstARM32ThreeAddrGPR<InstARM32::Asr> InstARM32Asr;
 typedef InstARM32ThreeAddrGPR<InstARM32::Bic> InstARM32Bic;
 typedef InstARM32ThreeAddrGPR<InstARM32::Eor> InstARM32Eor;
 typedef InstARM32ThreeAddrGPR<InstARM32::Lsl> InstARM32Lsl;
 typedef InstARM32ThreeAddrGPR<InstARM32::Lsr> InstARM32Lsr;
 typedef InstARM32ThreeAddrGPR<InstARM32::Mul> InstARM32Mul;
 typedef InstARM32ThreeAddrGPR<InstARM32::Orr> InstARM32Orr;
 typedef InstARM32ThreeAddrGPR<InstARM32::Rsb> InstARM32Rsb;
 typedef InstARM32ThreeAddrGPR<InstARM32::Sbc> InstARM32Sbc;
+typedef InstARM32ThreeAddrGPR<InstARM32::Sdiv> InstARM32Sdiv;
 typedef InstARM32ThreeAddrGPR<InstARM32::Sub> InstARM32Sub;
+typedef InstARM32ThreeAddrGPR<InstARM32::Udiv> InstARM32Udiv;
 // Move instruction (variable <- flex). This is more of a pseudo-inst.
 // If var is a register, then we use "mov". If var is stack, then we use
 // "str" to store to the stack.
 typedef InstARM32Movlike<InstARM32::Mov> InstARM32Mov;
 // MovT leaves the bottom bits alone so dest is also a source.
 // This helps indicate that a previous MovW setting dest is not dead code.
 typedef InstARM32TwoAddrGPR<InstARM32::Movt> InstARM32Movt;
 typedef InstARM32UnaryopGPR<InstARM32::Movw> InstARM32Movw;
 typedef InstARM32UnaryopGPR<InstARM32::Mvn> InstARM32Mvn;
 // Technically, the uxt{b,h} and sxt{b,h} instructions have a rotation
 // operand as well (rotate source by 8, 16, 24 bits prior to extending),
 // but we aren't using that for now, so just model as a Unaryop.
 typedef InstARM32UnaryopGPR<InstARM32::Sxt> InstARM32Sxt;
 typedef InstARM32UnaryopGPR<InstARM32::Uxt> InstARM32Uxt;
+typedef InstARM32FourAddrGPR<InstARM32::Mla> InstARM32Mla;
+typedef InstARM32FourAddrGPR<InstARM32::Mls> InstARM32Mls;
+
+// InstARM32Label represents an intra-block label that is the target
+// of an intra-block branch.  The offset between the label and the
+// branch must be fit in the instruction immediate (considered "near").
+class InstARM32Label : public InstARM32 {
+  InstARM32Label() = delete;
+  InstARM32Label(const InstARM32Label &) = delete;
+  InstARM32Label &operator=(const InstARM32Label &) = delete;
+
+public:
+  static InstARM32Label *create(Cfg *Func, TargetARM32 *Target) {
+    return new (Func->allocate<InstARM32Label>()) InstARM32Label(Func, Target);
+  }
+  uint32_t getEmitInstCount() const override { return 0; }
+  IceString getName(const Cfg *Func) const;
+  SizeT getNumber() const { return Number; }
+  void emit(const Cfg *Func) const override;
+  void emitIAS(const Cfg *Func) const override;
+  void dump(const Cfg *Func) const override;
+
+private:
+  InstARM32Label(Cfg *Func, TargetARM32 *Target);
+
+  SizeT Number; // used for unique label generation.
+};
 
 // Direct branch instruction.
 class InstARM32Br : public InstARM32Pred {
   InstARM32Br() = delete;
   InstARM32Br(const InstARM32Br &) = delete;
   InstARM32Br &operator=(const InstARM32Br &) = delete;
 
 public:
   // Create a conditional branch to one of two nodes.
   static InstARM32Br *create(Cfg *Func, CfgNode *TargetTrue,
                              CfgNode *TargetFalse, CondARM32::Cond Predicate) {
     assert(Predicate != CondARM32::AL);
+    const InstARM32Label *NoLabel = nullptr;
     return new (Func->allocate<InstARM32Br>())
-        InstARM32Br(Func, TargetTrue, TargetFalse, Predicate);
+        InstARM32Br(Func, TargetTrue, TargetFalse, NoLabel, Predicate);
   }
   // Create an unconditional branch to a node.
   static InstARM32Br *create(Cfg *Func, CfgNode *Target) {
     const CfgNode *NoCondTarget = nullptr;
+    const InstARM32Label *NoLabel = nullptr;
     return new (Func->allocate<InstARM32Br>())
-        InstARM32Br(Func, NoCondTarget, Target, CondARM32::AL);
+        InstARM32Br(Func, NoCondTarget, Target, NoLabel, CondARM32::AL);
   }
   // Create a non-terminator conditional branch to a node, with a
   // fallthrough to the next instruction in the current node.  This is
   // used for switch lowering.
   static InstARM32Br *create(Cfg *Func, CfgNode *Target,
                              CondARM32::Cond Predicate) {
     assert(Predicate != CondARM32::AL);
     const CfgNode *NoUncondTarget = nullptr;
+    const InstARM32Label *NoLabel = nullptr;
     return new (Func->allocate<InstARM32Br>())
-        InstARM32Br(Func, Target, NoUncondTarget, Predicate);
+        InstARM32Br(Func, Target, NoUncondTarget, NoLabel, Predicate);
+  }
+  // Create a conditional intra-block branch (or unconditional, if
+  // Condition==AL) to a label in the current block.
+  static InstARM32Br *create(Cfg *Func, InstARM32Label *Label,
+                             CondARM32::Cond Predicate) {
+    const CfgNode *NoCondTarget = nullptr;
+    const CfgNode *NoUncondTarget = nullptr;
+    return new (Func->allocate<InstARM32Br>())
+        InstARM32Br(Func, NoCondTarget, NoUncondTarget, Label, Predicate);
   }
   const CfgNode *getTargetTrue() const { return TargetTrue; }
   const CfgNode *getTargetFalse() const { return TargetFalse; }
   bool optimizeBranch(const CfgNode *NextNode);
   uint32_t getEmitInstCount() const override {
     uint32_t Sum = 0;
+    if (Label)
+      ++Sum;
     if (getTargetTrue())
       ++Sum;
     if (getTargetFalse())
       ++Sum;
     return Sum;
   }
   bool isUnconditionalBranch() const override {
     return getPredicate() == CondARM32::AL;
   }
   bool repointEdge(CfgNode *OldNode, CfgNode *NewNode) override;
   void emit(const Cfg *Func) const override;
   void emitIAS(const Cfg *Func) const override;
   void dump(const Cfg *Func) const override;
   static bool classof(const Inst *Inst) { return isClassof(Inst, Br); }
 
 private:
   InstARM32Br(Cfg *Func, const CfgNode *TargetTrue, const CfgNode *TargetFalse,
-              CondARM32::Cond Predicate);
+              const InstARM32Label *Label, CondARM32::Cond Predicate);
 
   const CfgNode *TargetTrue;
   const CfgNode *TargetFalse;
+  const InstARM32Label *Label; // Intra-block branch target
 };
 
 // AdjustStack instruction - subtracts SP by the given amount and
 // updates the stack offset during code emission.
 class InstARM32AdjustStack : public InstARM32 {
   InstARM32AdjustStack() = delete;
   InstARM32AdjustStack(const InstARM32AdjustStack &) = delete;
   InstARM32AdjustStack &operator=(const InstARM32AdjustStack &) = delete;
 
 public:
@@ skipping 78 matching lines @@
   void emit(const Cfg *Func) const override;
   void emitIAS(const Cfg *Func) const override;
   void dump(const Cfg *Func) const override;
   static bool classof(const Inst *Inst) { return isClassof(Inst, Ldr); }
 
 private:
   InstARM32Ldr(Cfg *Func, Variable *Dest, OperandARM32Mem *Mem,
                CondARM32::Cond Predicate);
 };
 
-// Multiply Accumulate: d := x * y + a
-class InstARM32Mla : public InstARM32Pred {
-  InstARM32Mla() = delete;
-  InstARM32Mla(const InstARM32Mla &) = delete;
-  InstARM32Mla &operator=(const InstARM32Mla &) = delete;
-
-public:
-  // Everything must be a register.
-  static InstARM32Mla *create(Cfg *Func, Variable *Dest, Variable *Src0,
-                              Variable *Src1, Variable *Acc,
-                              CondARM32::Cond Predicate) {
-    return new (Func->allocate<InstARM32Mla>())
-        InstARM32Mla(Func, Dest, Src0, Src1, Acc, Predicate);
-  }
-  void emit(const Cfg *Func) const override;
-  void emitIAS(const Cfg *Func) const override;
-  void dump(const Cfg *Func) const override;
-  static bool classof(const Inst *Inst) { return isClassof(Inst, Mla); }
-
-private:
-  InstARM32Mla(Cfg *Func, Variable *Dest, Variable *Src0, Variable *Src1,
-               Variable *Acc, CondARM32::Cond Predicate);
-};
-
 // Pop into a list of GPRs. Technically this can be predicated, but we don't
 // need that functionality.
 class InstARM32Pop : public InstARM32 {
   InstARM32Pop() = delete;
   InstARM32Pop(const InstARM32Pop &) = delete;
   InstARM32Pop &operator=(const InstARM32Pop &) = delete;
 
 public:
   static InstARM32Pop *create(Cfg *Func, const VarList &Dests) {
     return new (Func->allocate<InstARM32Pop>()) InstARM32Pop(Func, Dests);
@@ skipping 74 matching lines @@
   void emit(const Cfg *Func) const override;
   void emitIAS(const Cfg *Func) const override;
   void dump(const Cfg *Func) const override;
   static bool classof(const Inst *Inst) { return isClassof(Inst, Str); }
 
 private:
   InstARM32Str(Cfg *Func, Variable *Value, OperandARM32Mem *Mem,
                CondARM32::Cond Predicate);
 };
 
+class InstARM32Trap : public InstARM32 {
+  InstARM32Trap() = delete;
+  InstARM32Trap(const InstARM32Trap &) = delete;
+  InstARM32Trap &operator=(const InstARM32Trap &) = delete;
+
+public:
+  static InstARM32Trap *create(Cfg *Func) {
+    return new (Func->allocate<InstARM32Trap>()) InstARM32Trap(Func);
+  }
+  void emit(const Cfg *Func) const override;
+  void emitIAS(const Cfg *Func) const override;
+  void dump(const Cfg *Func) const override;
+  static bool classof(const Inst *Inst) { return isClassof(Inst, Trap); }
+
+private:
+  explicit InstARM32Trap(Cfg *Func);
+};
+
+class InstARM32Tst : public InstARM32Pred {
+  InstARM32Tst() = delete;
+  InstARM32Tst(const InstARM32Tst &) = delete;
+  InstARM32Tst &operator=(const InstARM32Tst &) = delete;
+
+public:
+  static InstARM32Tst *create(Cfg *Func, Variable *Src0, Operand *Src1,
+                              CondARM32::Cond Predicate) {
+    return new (Func->allocate<InstARM32Tst>())
+        InstARM32Tst(Func, Src0, Src1, Predicate);
+  }
+  void emit(const Cfg *Func) const override;
+  void emitIAS(const Cfg *Func) const override;
+  void dump(const Cfg *Func) const override;
+  static bool classof(const Inst *Inst) { return isClassof(Inst, Tst); }
+
+private:
+  InstARM32Tst(Cfg *Func, Variable *Src0, Operand *Src1,
+               CondARM32::Cond Predicate);
+};
+
 // Unsigned Multiply Long: d.lo, d.hi := x * y
 class InstARM32Umull : public InstARM32Pred {
   InstARM32Umull() = delete;
   InstARM32Umull(const InstARM32Umull &) = delete;
   InstARM32Umull &operator=(const InstARM32Umull &) = delete;
 
 public:
   // Everything must be a register.
   static InstARM32Umull *create(Cfg *Func, Variable *DestLo, Variable *DestHi,
                                 Variable *Src0, Variable *Src1,
@@ skipping 16 matching lines @@
 // Declare partial template specializations of emit() methods that
 // already have default implementations.  Without this, there is the
 // possibility of ODR violations and link errors.
 
 template <> void InstARM32Movw::emit(const Cfg *Func) const;
 template <> void InstARM32Movt::emit(const Cfg *Func) const;
 
 } // end of namespace Ice
 
 #endif // SUBZERO_SRC_ICEINSTARM32_H