ARM lowering integer divide and remainder, with div by 0 checks.

tests_lit/llvm2ice_tests/arith.ll

 ; Assembly test for simple arithmetic operations.
 
 ; RUN: %if --need=target_X8632 --command %p2i --filetype=obj --disassemble \
 ; RUN:   --target x8632 -i %s --args -O2 \
 ; RUN:   | %if --need=target_X8632 --command FileCheck %s
 
 ; TODO(jvoung): Stop skipping unimplemented parts (via --skip-unimplemented)
 ; once enough infrastructure is in. Also, switch to --filetype=obj
 ; when possible.
 ; RUN: %if --need=target_ARM32 --need=allow_dump \
-; RUN:   --command %p2i --filetype=asm --assemble \
-; RUN:   --disassemble --target arm32 -i %s --args -O2 --skip-unimplemented \
+; RUN:   --command %p2i --filetype=asm --assemble --disassemble --target arm32 \
+; RUN:   -i %s --args -O2 --skip-unimplemented \
 ; RUN:   | %if --need=target_ARM32 --need=allow_dump \
 ; RUN:   --command FileCheck --check-prefix ARM32 %s
+; RUN: %if --need=target_ARM32 --need=allow_dump \
+; RUN:   --command %p2i --filetype=asm --assemble --disassemble --target arm32 \
+; RUN:   -i %s --args -O2 --mattr=hwdiv-arm --skip-unimplemented \
+; RUN:   | %if --need=target_ARM32 --need=allow_dump \
+; RUN:   --command FileCheck --check-prefix ARM32HWDIV %s
 
 define i32 @Add(i32 %a, i32 %b) {
 entry:
   %add = add i32 %b, %a
   ret i32 %add
 }
 ; CHECK-LABEL: Add
 ; CHECK: add e
 ; ARM32-LABEL: Add
 ; ARM32: add r
@@ skipping 85 matching lines @@
 ; ARM32: add r
 
 define i32 @Sdiv(i32 %a, i32 %b) {
 entry:
   %div = sdiv i32 %a, %b
   ret i32 %div
 }
 ; CHECK-LABEL: Sdiv
 ; CHECK: cdq
 ; CHECK: idiv e
+;
 ; ARM32-LABEL: Sdiv
-; TODO(jvoung) -- implement divide and check here.
-; The lowering needs to check if the denominator is 0 and trap, since
-; ARM normally doesn't trap on divide by 0.
+; ARM32: tst [[DENOM:r.*]], [[DENOM]]
+; ARM32: bne [[LABEL:[0-9a-f]+]]
+; ARM32: .word 0xe7fedef0
+; ARM32: [[LABEL]]: {{.*}} bl {{.*}} __divsi3
+; ARM32HWDIV-LABEL: Sdiv
+; ARM32HWDIV: tst
+; ARM32HWDIV: bne
+; ARM32HWDIV: sdiv
+
+define i32 @SdivConst(i32 %a) {
+entry:
+  %div = sdiv i32 %a, 219
+  ret i32 %div
+}
+; CHECK-LABEL: SdivConst
+; CHECK: cdq
+; CHECK: idiv e
+;
+; ARM32-LABEL: SdivConst
+; ARM32-NOT: tst
+; ARM32: bl {{.*}} __divsi3
+; ARM32HWDIV-LABEL: SdivConst
+; ARM32HWDIV-NOT: tst
+; ARM32HWDIV: sdiv
 
 define i32 @Srem(i32 %a, i32 %b) {
 entry:
   %rem = srem i32 %a, %b
   ret i32 %rem
 }
 ; CHECK-LABEL: Srem
 ; CHECK: cdq
 ; CHECK: idiv e
+;
 ; ARM32-LABEL: Srem
+; ARM32: tst [[DENOM:r.*]], [[DENOM]]
+; ARM32: bne
+; ARM32: bl {{.*}} __modsi3
+; ARM32HWDIV-LABEL: Srem
+; ARM32HWDIV: tst
+; ARM32HWDIV: bne
+; ARM32HWDIV: sdiv
+; ARM32HWDIV: mls
 
 define i32 @Udiv(i32 %a, i32 %b) {
 entry:
   %div = udiv i32 %a, %b
   ret i32 %div
 }
 ; CHECK-LABEL: Udiv
 ; CHECK: div e
+;
 ; ARM32-LABEL: Udiv
+; ARM32: tst [[DENOM:r.*]], [[DENOM]]
+; ARM32: bne
+; ARM32: bl {{.*}} __udivsi3
+; ARM32HWDIV-LABEL: Udiv
+; ARM32HWDIV: tst
+; ARM32HWDIV: bne
+; ARM32HWDIV: udiv
 
 define i32 @Urem(i32 %a, i32 %b) {
 entry:
   %rem = urem i32 %a, %b
   ret i32 %rem
 }
 ; CHECK-LABEL: Urem
 ; CHECK: div e
+;
 ; ARM32-LABEL: Urem
+; ARM32: tst [[DENOM:r.*]], [[DENOM]]
+; ARM32: bne
+; ARM32: bl {{.*}} __umodsi3
+; ARM32HWDIV-LABEL: Urem
+; ARM32HWDIV: tst
+; ARM32HWDIV: bne
+; ARM32HWDIV: udiv
+; ARM32HWDIV: mls