ARM lowering integer divide and remainder, with div by 0 checks.

tests_lit/llvm2ice_tests/64bit.pnacl.ll

 ; This tries to be a comprehensive test of i64 operations, in
 ; particular the patterns for lowering i64 operations into constituent
 ; i32 operations on x86-32.
 
 ; RUN: %if --need=target_X8632 --command %p2i --filetype=obj --disassemble \
 ; RUN:   --target x8632 -i %s --args -O2 \
 ; RUN:   | %if --need=target_X8632 --command FileCheck %s
 
 ; RUN: %if --need=target_X8632 --command %p2i --filetype=obj --disassemble \
 ; RUN:   --target x8632 -i %s --args -Om1 \
@@ skipping 297 matching lines @@
 define internal i64 @div64BitSigned(i64 %a, i64 %b) {
 entry:
   %div = sdiv i64 %a, %b
   ret i64 %div
 }
 ; CHECK-LABEL: div64BitSigned
 ; CHECK: call {{.*}} R_{{.*}}    __divdi3
 
 ; OPTM1-LABEL: div64BitSigned
 ; OPTM1: call {{.*}} R_{{.*}}    __divdi3
+;
+; ARM32-LABEL: div64BitSigned
+; ARM32: orrs {{r.*}}, {{r.*}}
+; ARM32: bne
+; ARM32: bl {{.*}} __divdi3
 
 define internal i64 @div64BitSignedConst(i64 %a) {
 entry:
   %div = sdiv i64 %a, 12345678901234
   ret i64 %div
 }
 ; CHECK-LABEL: div64BitSignedConst
 ; CHECK: mov     DWORD PTR [esp+0xc],0xb3a
 ; CHECK: mov     DWORD PTR [esp+0x8],0x73ce2ff2
 ; CHECK: call {{.*}} R_{{.*}}    __divdi3
 ;
 ; OPTM1-LABEL: div64BitSignedConst
 ; OPTM1: mov     DWORD PTR [esp+0xc],0xb3a
 ; OPTM1: mov     DWORD PTR [esp+0x8],0x73ce2ff2
 ; OPTM1: call {{.*}} R_{{.*}}    __divdi3
+;
+; ARM32-LABEL: div64BitSignedConst
+; For a constant, we should be able to optimize-out the divide by zero check.
+; ARM32-NOT: orrs
+; ARM32: movw {{.*}} ; 0x2ff2
+; ARM32: movt {{.*}} ; 0x73ce
+; ARM32: movw {{.*}} ; 0xb3a
+; ARM32: bl {{.*}} __divdi3
 
 define internal i64 @div64BitUnsigned(i64 %a, i64 %b) {
 entry:
   %div = udiv i64 %a, %b
   ret i64 %div
 }
 ; CHECK-LABEL: div64BitUnsigned
 ; CHECK: call {{.*}} R_{{.*}}    __udivdi3
 ;
 ; OPTM1-LABEL: div64BitUnsigned
 ; OPTM1: call {{.*}} R_{{.*}}    __udivdi3
+;
+; ARM32-LABEL: div64BitUnsigned
+; ARM32: orrs {{r.*}}, {{r.*}}
+; ARM32: bne
+; ARM32: bl {{.*}} __udivdi3
 
 define internal i64 @rem64BitSigned(i64 %a, i64 %b) {
 entry:
   %rem = srem i64 %a, %b
   ret i64 %rem
 }
 ; CHECK-LABEL: rem64BitSigned
 ; CHECK: call {{.*}} R_{{.*}}    __moddi3
 ;
 ; OPTM1-LABEL: rem64BitSigned
 ; OPTM1: call {{.*}} R_{{.*}}    __moddi3
+;
+; ARM32-LABEL: rem64BitSigned
+; ARM32: orrs {{r.*}}, {{r.*}}
+; ARM32: bne
+; ARM32: bl {{.*}} __moddi3
 
 define internal i64 @rem64BitUnsigned(i64 %a, i64 %b) {
 entry:
   %rem = urem i64 %a, %b
   ret i64 %rem
 }
 ; CHECK-LABEL: rem64BitUnsigned
 ; CHECK: call {{.*}} R_{{.*}}    __umoddi3
 ;
 ; OPTM1-LABEL: rem64BitUnsigned
 ; OPTM1: call {{.*}} R_{{.*}}    __umoddi3
+;
+; ARM32-LABEL: rem64BitUnsigned
+; ARM32: orrs {{r.*}}, {{r.*}}
+; ARM32: bne
+; ARM32: bl {{.*}} __umoddi3
 
 define internal i64 @shl64BitSigned(i64 %a, i64 %b) {
 entry:
   %shl = shl i64 %a, %b
   ret i64 %shl
 }
 ; CHECK-LABEL: shl64BitSigned
 ; CHECK: shld
 ; CHECK: shl e
 ; CHECK: test {{.*}},0x20
@@ skipping 1339 matching lines @@
   ret void
 }
 ; The following checks are not strictly necessary since one of the RUN
 ; lines actually runs the output through the assembler.
 ; CHECK-LABEL: icmpLt64Imm
 ; CHECK-NOT: cmp 0x{{[0-9a-f]+}},
 ; OPTM1-LABEL: icmpLt64Imm
 ; OPTM1-NOT: cmp 0x{{[0-9a-f]+}},
 ; ARM32-LABEL: icmpLt64Imm
 ; ARM32-NOT: cmp #{{[0-9a-f]+}},