MIPS: Disassembler enhancement. Disassembled branch instruction displays branch target absolute add…

src/mips/disasm-mips.cc

 // Copyright 2012 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 // A Disassembler object is used to disassemble a block of code instruction by
 // instruction. The default implementation of the NameConverter object can be
 // overriden to modify register names or to do symbol lookup on addresses.
 //
 // The example below will disassemble a block of code and print it to stdout.
 //
@@ skipping 69 matching lines @@
   void PrintSs1(Instruction* instr);
   void PrintSs2(Instruction* instr);
   void PrintBc(Instruction* instr);
   void PrintCc(Instruction* instr);
   void PrintBp2(Instruction* instr);
   void PrintFunction(Instruction* instr);
   void PrintSecondaryField(Instruction* instr);
   void PrintUImm16(Instruction* instr);
   void PrintSImm16(Instruction* instr);
   void PrintXImm16(Instruction* instr);
+  void PrintPCImm16(Instruction* instr, int delta_pc, int n_bits);
   void PrintXImm18(Instruction* instr);
   void PrintSImm18(Instruction* instr);
   void PrintXImm19(Instruction* instr);
   void PrintSImm19(Instruction* instr);
   void PrintXImm21(Instruction* instr);
   void PrintSImm21(Instruction* instr);
+  void PrintPCImm21(Instruction* instr, int delta_pc, int n_bits);
   void PrintXImm26(Instruction* instr);
   void PrintSImm26(Instruction* instr);
+  void PrintPCImm26(Instruction* instr, int delta_pc, int n_bits);
+  void PrintPCImm26(Instruction* instr);
   void PrintCode(Instruction* instr);   // For break and trap instructions.
   void PrintFormat(Instruction* instr);  // For floating format postfix.
   // Printing of instruction name.
   void PrintInstructionName(Instruction* instr);
 
   // Handle formatting of instructions and their options.
   int FormatRegister(Instruction* instr, const char* option);
   int FormatFPURegister(Instruction* instr, const char* option);
   int FormatOption(Instruction* instr, const char* option);
   void Format(Instruction* instr, const char* format);
@@ skipping 155 matching lines @@
 }
 
 
 // Print 16-bit hexa immediate value.
 void Decoder::PrintXImm16(Instruction* instr) {
   int32_t imm = instr->Imm16Value();
   out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "0x%x", imm);
 }
 
 
+// Print absoulte address for 16-bit offset or immediate value.
+// The absolute address is calculated according following expression:
+//      PC + delta_pc + (offset << n_bits)
+void Decoder::PrintPCImm16(Instruction* instr, int delta_pc, int n_bits) {
+  int16_t offset = instr->Imm16Value();
+  out_buffer_pos_ +=
+      SNPrintF(out_buffer_ + out_buffer_pos_, "%s",
+               converter_.NameOfAddress(reinterpret_cast<byte*>(instr) +
+                                        delta_pc + (offset << n_bits)));
+}
+
+
 // Print 18-bit signed immediate value.
 void Decoder::PrintSImm18(Instruction* instr) {
   int32_t imm =
       ((instr->Imm18Value()) << (32 - kImm18Bits)) >> (32 - kImm18Bits);
   out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "%d", imm);
 }
 
 
 // Print 18-bit hexa immediate value.
 void Decoder::PrintXImm18(Instruction* instr) {
@@ skipping 29 matching lines @@
 // Print 21-bit signed immediate value.
 void Decoder::PrintSImm21(Instruction* instr) {
   int32_t imm21 = instr->Imm21Value();
   // set sign
   imm21 <<= (32 - kImm21Bits);
   imm21 >>= (32 - kImm21Bits);
   out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "%d", imm21);
 }
 
 
+// Print absoulte address for 21-bit offset or immediate value.
+// The absolute address is calculated according following expression:
+//      PC + delta_pc + (offset << n_bits)
+void Decoder::PrintPCImm21(Instruction* instr, int delta_pc, int n_bits) {
+  int32_t imm21 = instr->Imm21Value();
+  // set sign
+  imm21 <<= (32 - kImm21Bits);
+  imm21 >>= (32 - kImm21Bits);
+  out_buffer_pos_ +=
+      SNPrintF(out_buffer_ + out_buffer_pos_, "%s",
+               converter_.NameOfAddress(reinterpret_cast<byte*>(instr) +
+                                        delta_pc + (imm21 << n_bits)));
+}
+
+
 // Print 26-bit hex immediate value.
 void Decoder::PrintXImm26(Instruction* instr) {
   uint32_t imm = instr->Imm26Value() << kImmFieldShift;
   out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "0x%x", imm);
 }
 
 
 // Print 26-bit signed immediate value.
 void Decoder::PrintSImm26(Instruction* instr) {
   int32_t imm26 = instr->Imm26Value();
   // set sign
   imm26 <<= (32 - kImm26Bits);
   imm26 >>= (32 - kImm26Bits);
   out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "%d", imm26);
 }
 
 
+// Print absoulte address for 26-bit offset or immediate value.
+// The absolute address is calculated according following expression:
+//      PC + delta_pc + (offset << n_bits)
+void Decoder::PrintPCImm26(Instruction* instr, int delta_pc, int n_bits) {
+  int32_t imm26 = instr->Imm26Value();
+  // set sign
+  imm26 <<= (32 - kImm26Bits);
+  imm26 >>= (32 - kImm26Bits);
+  out_buffer_pos_ +=
+      SNPrintF(out_buffer_ + out_buffer_pos_, "%s",
+               converter_.NameOfAddress(reinterpret_cast<byte*>(instr) +
+                                        delta_pc + (imm26 << n_bits)));
+}
+
+
+// Print absoulte address for 26-bit offset or immediate value.
+// The absolute address is calculated according following expression:
+//      PC[GPRLEN-1 .. 28] || instr_index26 || 00
+void Decoder::PrintPCImm26(Instruction* instr) {
+  int32_t imm26 = instr->Imm26Value();
+  uint32_t pc_mask = ~0xfffffff;
+  uint32_t pc = ((uint32_t)(instr + 1) & pc_mask) | (imm26 << 2);
+  out_buffer_pos_ +=
+      SNPrintF(out_buffer_ + out_buffer_pos_, "%s",
+               converter_.NameOfAddress((reinterpret_cast<byte*>(pc))));
+}
+
+
 // Print 26-bit immediate value.
 void Decoder::PrintCode(Instruction* instr) {
   if (instr->OpcodeFieldRaw() != SPECIAL)
     return;  // Not a break or trap instruction.
   switch (instr->FunctionFieldRaw()) {
     case BREAK: {
       int32_t code = instr->Bits(25, 6);
       out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_,
                                   "0x%05x (%d)", code, code);
       break;
@@ skipping 113 matching lines @@
               PrintSImm16(instr);
               break;
             case 'u':
               DCHECK(STRING_STARTS_WITH(format, "imm16u"));
               PrintSImm16(instr);
               break;
             case 'x':
               DCHECK(STRING_STARTS_WITH(format, "imm16x"));
               PrintXImm16(instr);
               break;
+            case 'p': {  // The PC relative address.
+              DCHECK(STRING_STARTS_WITH(format, "imm16p"));
+              int delta_pc = 0;
+              int n_bits = 0;
+              switch (format[6]) {
+                case '4': {
+                  DCHECK(STRING_STARTS_WITH(format, "imm16p4"));
+                  delta_pc = 4;
+                  switch (format[8]) {
+                    case '2':
+                      DCHECK(STRING_STARTS_WITH(format, "imm16p4s2"));
+                      n_bits = 2;
+                      PrintPCImm16(instr, delta_pc, n_bits);
+                      return 9;
+                  }
+                }
+              }
+            }
           }
           return 6;
         } else if (format[4] == '8') {
           DCHECK(STRING_STARTS_WITH(format, "imm18"));
           switch (format[5]) {
             case 's':
               DCHECK(STRING_STARTS_WITH(format, "imm18s"));
               PrintSImm18(instr);
               break;
             case 'x':
@@ skipping 20 matching lines @@
         DCHECK(STRING_STARTS_WITH(format, "imm21"));
         switch (format[5]) {
           case 's':
             DCHECK(STRING_STARTS_WITH(format, "imm21s"));
             PrintSImm21(instr);
             break;
           case 'x':
             DCHECK(STRING_STARTS_WITH(format, "imm21x"));
             PrintXImm21(instr);
             break;
+          case 'p': {  // The PC relative address.
+            DCHECK(STRING_STARTS_WITH(format, "imm21p"));
+            int delta_pc = 0;
+            int n_bits = 0;
+            switch (format[6]) {
+              case '4': {
+                DCHECK(STRING_STARTS_WITH(format, "imm21p4"));
+                delta_pc = 4;
+                switch (format[8]) {
+                  case '2':
+                    DCHECK(STRING_STARTS_WITH(format, "imm21p4s2"));
+                    n_bits = 2;
+                    PrintPCImm21(instr, delta_pc, n_bits);
+                    return 9;
+                }
+              }
+            }
+          }
         }
         return 6;
       } else if (format[3] == '2' && format[4] == '6') {
         DCHECK(STRING_STARTS_WITH(format, "imm26"));
         switch (format[5]) {
           case 's':
             DCHECK(STRING_STARTS_WITH(format, "imm26s"));
             PrintSImm26(instr);
             break;
           case 'x':
             DCHECK(STRING_STARTS_WITH(format, "imm26x"));
             PrintXImm26(instr);
             break;
+          case 'p': {  // The PC relative address.
+            DCHECK(STRING_STARTS_WITH(format, "imm26p"));
+            int delta_pc = 0;
+            int n_bits = 0;
+            switch (format[6]) {
+              case '4': {
+                DCHECK(STRING_STARTS_WITH(format, "imm26p4"));
+                delta_pc = 4;
+                switch (format[8]) {
+                  case '2':
+                    DCHECK(STRING_STARTS_WITH(format, "imm26p4s2"));
+                    n_bits = 2;
+                    PrintPCImm26(instr, delta_pc, n_bits);
+                    return 9;
+                }
+              }
+            }
+          }
+          case 'j': {  // Absolute address for jump instructions.
+            DCHECK(STRING_STARTS_WITH(format, "imm26j"));
+            PrintPCImm26(instr);
+            break;
+          }
         }
         return 6;
       }
     }
     case 'r': {   // 'r: registers.
       return FormatRegister(instr, format);
     }
     case 'f': {   // 'f: FPUregisters.
       return FormatFPURegister(instr, format);
     }
@@ skipping 658 matching lines @@
   }
 }
 
 
 void Decoder::DecodeTypeImmediate(Instruction* instr) {
   switch (instr->OpcodeFieldRaw()) {
     case COP1:
       switch (instr->RsFieldRaw()) {
         case BC1:
           if (instr->FBtrueValue()) {
-            Format(instr, "bc1t    'bc, 'imm16u");
+            Format(instr, "bc1t    'bc, 'imm16u -> 'imm16p4s2");
           } else {
-            Format(instr, "bc1f    'bc, 'imm16u");
+            Format(instr, "bc1f    'bc, 'imm16u -> 'imm16p4s2");
           }
           break;
         case BC1EQZ:
-          Format(instr, "bc1eqz    'ft, 'imm16u");
+          Format(instr, "bc1eqz    'ft, 'imm16u -> 'imm16p4s2");
           break;
         case BC1NEZ:
-          Format(instr, "bc1nez    'ft, 'imm16u");
+          Format(instr, "bc1nez    'ft, 'imm16u -> 'imm16p4s2");
           break;
         default:
           UNREACHABLE();
       }
 
       break;  // Case COP1.
     // ------------- REGIMM class.
     case REGIMM:
       switch (instr->RtFieldRaw()) {
         case BLTZ:
-          Format(instr, "bltz    'rs, 'imm16u");
+          Format(instr, "bltz    'rs, 'imm16u -> 'imm16p4s2");
           break;
         case BLTZAL:
-          Format(instr, "bltzal  'rs, 'imm16u");
+          Format(instr, "bltzal  'rs, 'imm16u -> 'imm16p4s2");
           break;
         case BGEZ:
-          Format(instr, "bgez    'rs, 'imm16u");
+          Format(instr, "bgez    'rs, 'imm16u -> 'imm16p4s2");
           break;
         case BGEZAL:
-          Format(instr, "bgezal  'rs, 'imm16u");
+          Format(instr, "bgezal  'rs, 'imm16u -> 'imm16p4s2");
           break;
         case BGEZALL:
-          Format(instr, "bgezall 'rs, 'imm16u");
+          Format(instr, "bgezall 'rs, 'imm16u -> 'imm16p4s2");
           break;
         default:
           UNREACHABLE();
       }
     break;  // Case REGIMM.
     // ------------- Branch instructions.
     case BEQ:
-      Format(instr, "beq     'rs, 'rt, 'imm16u");
+      Format(instr, "beq     'rs, 'rt, 'imm16u -> 'imm16p4s2");
       break;
     case BC:
-      Format(instr, "bc      'imm26s");
+      Format(instr, "bc      'imm26s -> 'imm26p4s2");
       break;
     case BALC:
-      Format(instr, "balc    'imm26s");
+      Format(instr, "balc    'imm26s -> 'imm26p4s2");
       break;
     case BNE:
-      Format(instr, "bne     'rs, 'rt, 'imm16u");
+      Format(instr, "bne     'rs, 'rt, 'imm16u -> 'imm16p4s2");
       break;
     case BLEZ:
-      if ((instr->RtFieldRaw() == 0)
-          && (instr->RsFieldRaw() != 0)) {
-        Format(instr, "blez    'rs, 'imm16u");
-      } else if ((instr->RtFieldRaw() != instr->RsFieldRaw())
-          && (instr->RsFieldRaw() != 0) && (instr->RtFieldRaw() != 0)) {
-        Format(instr, "bgeuc    'rs, 'rt, 'imm16u");
-      } else if ((instr->RtFieldRaw() == instr->RsFieldRaw())
-          && (instr->RtFieldRaw() != 0)) {
-        Format(instr, "bgezalc  'rs, 'imm16u");
-      } else if ((instr->RsFieldRaw() == 0)
-          && (instr->RtFieldRaw() != 0)) {
-        Format(instr, "blezalc  'rs, 'imm16u");
+      if ((instr->RtValue() == 0) && (instr->RsValue() != 0)) {
+        Format(instr, "blez    'rs, 'imm16u -> 'imm16p4s2");
+      } else if ((instr->RtValue() != instr->RsValue()) &&
+                 (instr->RsValue() != 0) && (instr->RtValue() != 0)) {
+        Format(instr, "bgeuc    'rs, 'rt, 'imm16u -> 'imm16p4s2");
+      } else if ((instr->RtValue() == instr->RsValue()) &&
+                 (instr->RtValue() != 0)) {
+        Format(instr, "bgezalc  'rs, 'imm16u -> 'imm16p4s2");
+      } else if ((instr->RsValue() == 0) && (instr->RtValue() != 0)) {
+        Format(instr, "blezalc  'rt, 'imm16u -> 'imm16p4s2");
       } else {
         UNREACHABLE();
       }
       break;
     case BGTZ:
-      if ((instr->RtFieldRaw() == 0)
-          && (instr->RsFieldRaw() != 0)) {
-        Format(instr, "bgtz    'rs, 'imm16u");
-      } else if ((instr->RtFieldRaw() != instr->RsFieldRaw())
-          && (instr->RsFieldRaw() != 0) && (instr->RtFieldRaw() != 0)) {
-        Format(instr, "bltuc   'rs, 'rt, 'imm16u");
-      } else if ((instr->RtFieldRaw() == instr->RsFieldRaw())
-          && (instr->RtFieldRaw() != 0)) {
-        Format(instr, "bltzalc 'rt, 'imm16u");
-      } else if ((instr->RsFieldRaw() == 0)
-          && (instr->RtFieldRaw() != 0)) {
-        Format(instr, "bgtzalc 'rt, 'imm16u");
+      if ((instr->RtValue() == 0) && (instr->RsValue() != 0)) {
+        Format(instr, "bgtz    'rs, 'imm16u -> 'imm16p4s2");
+      } else if ((instr->RtValue() != instr->RsValue()) &&
+                 (instr->RsValue() != 0) && (instr->RtValue() != 0)) {
+        Format(instr, "bltuc   'rs, 'rt, 'imm16u -> 'imm16p4s2");
+      } else if ((instr->RtValue() == instr->RsValue()) &&
+                 (instr->RtValue() != 0)) {
+        Format(instr, "bltzalc 'rt, 'imm16u -> 'imm16p4s2");
+      } else if ((instr->RsValue() == 0) && (instr->RtValue() != 0)) {
+        Format(instr, "bgtzalc 'rt, 'imm16u -> 'imm16p4s2");
       } else {
         UNREACHABLE();
       }
       break;
     case BLEZL:
-      if ((instr->RtFieldRaw() == instr->RsFieldRaw())
-          && (instr->RtFieldRaw() != 0)) {
-        Format(instr, "bgezc    'rt, 'imm16u");
-      } else if ((instr->RtFieldRaw() != instr->RsFieldRaw())
-          && (instr->RsFieldRaw() != 0) && (instr->RtFieldRaw() != 0)) {
-        Format(instr, "bgec     'rs, 'rt, 'imm16u");
-      } else if ((instr->RsFieldRaw() == 0)
-          && (instr->RtFieldRaw() != 0)) {
-        Format(instr, "blezc    'rt, 'imm16u");
+      if ((instr->RtValue() == instr->RsValue()) && (instr->RtValue() != 0)) {
+        Format(instr, "bgezc    'rt, 'imm16u -> 'imm16p4s2");
+      } else if ((instr->RtValue() != instr->RsValue()) &&
+                 (instr->RsValue() != 0) && (instr->RtValue() != 0)) {
+        Format(instr, "bgec     'rs, 'rt, 'imm16u -> 'imm16p4s2");
+      } else if ((instr->RsValue() == 0) && (instr->RtValue() != 0)) {
+        Format(instr, "blezc    'rt, 'imm16u -> 'imm16p4s2");
       } else {
         UNREACHABLE();
       }
       break;
     case BGTZL:
-      if ((instr->RtFieldRaw() == instr->RsFieldRaw())
-          && (instr->RtFieldRaw() != 0)) {
-        Format(instr, "bltzc    'rt, 'imm16u");
-      } else if ((instr->RtFieldRaw() != instr->RsFieldRaw())
-          && (instr->RsFieldRaw() != 0) && (instr->RtFieldRaw() != 0)) {
-        Format(instr, "bltc     'rs, 'rt, 'imm16u");
-      } else if ((instr->RsFieldRaw() == 0)
-          && (instr->RtFieldRaw() != 0)) {
-        Format(instr, "bgtzc    'rt, 'imm16u");
+      if ((instr->RtValue() == instr->RsValue()) && (instr->RtValue() != 0)) {
+        Format(instr, "bltzc    'rt, 'imm16u -> 'imm16p4s2");
+      } else if ((instr->RtValue() != instr->RsValue()) &&
+                 (instr->RsValue() != 0) && (instr->RtValue() != 0)) {
+        Format(instr, "bltc     'rs, 'rt, 'imm16u -> 'imm16p4s2");
+      } else if ((instr->RsValue() == 0) && (instr->RtValue() != 0)) {
+        Format(instr, "bgtzc    'rt, 'imm16u -> 'imm16p4s2");
       } else {
         UNREACHABLE();
       }
       break;
     case POP66:
       if (instr->RsValue() == JIC) {
         Format(instr, "jic     'rt, 'imm16s");
       } else {
-        Format(instr, "beqzc   'rs, 'imm21s");
+        Format(instr, "beqzc   'rs, 'imm21s -> 'imm21p4s2");
       }
       break;
     case POP76:
       if (instr->RsValue() == JIALC) {
         Format(instr, "jialc   'rt, 'imm16x");
       } else {
-        Format(instr, "bnezc   'rs, 'imm21x");
+        Format(instr, "bnezc   'rs, 'imm21x -> 'imm21p4s2");
       }
       break;
     // ------------- Arithmetic instructions.
     case ADDI:
       if (!IsMipsArchVariant(kMips32r6)) {
         Format(instr, "addi    'rt, 'rs, 'imm16s");
       } else {
         // Check if BOVC or BEQC instruction.
-        if (instr->RsFieldRaw() >= instr->RtFieldRaw()) {
-          Format(instr, "bovc  'rs, 'rt, 'imm16s");
-        } else if (instr->RsFieldRaw() < instr->RtFieldRaw()) {
-          Format(instr, "beqc  'rs, 'rt, 'imm16s");
+        if (instr->RsValue() >= instr->RtValue()) {
+          Format(instr, "bovc  'rs, 'rt, 'imm16s -> 'imm16p4s2");
+        } else if (instr->RsValue() < instr->RtValue()) {
+          Format(instr, "beqc  'rs, 'rt, 'imm16s -> 'imm16p4s2");
         } else {
           UNREACHABLE();
         }
       }
       break;
     case DADDI:
       if (IsMipsArchVariant(kMips32r6)) {
         // Check if BNVC or BNEC instruction.
-        if (instr->RsFieldRaw() >= instr->RtFieldRaw()) {
-          Format(instr, "bnvc  'rs, 'rt, 'imm16s");
-        } else if (instr->RsFieldRaw() < instr->RtFieldRaw()) {
-          Format(instr, "bnec  'rs, 'rt, 'imm16s");
+        if (instr->RsValue() >= instr->RtValue()) {
+          Format(instr, "bnvc  'rs, 'rt, 'imm16s -> 'imm16p4s2");
+        } else if (instr->RsValue() < instr->RtValue()) {
+          Format(instr, "bnec  'rs, 'rt, 'imm16s -> 'imm16p4s2");
         } else {
           UNREACHABLE();
         }
       }
       break;
     case ADDIU:
       Format(instr, "addiu   'rt, 'rs, 'imm16s");
       break;
     case SLTI:
       Format(instr, "slti    'rt, 'rs, 'imm16s");
@@ skipping 106 matching lines @@
       printf("a 0x%x \n", instr->OpcodeFieldRaw());
       UNREACHABLE();
       break;
   }
 }
 
 
 void Decoder::DecodeTypeJump(Instruction* instr) {
   switch (instr->OpcodeFieldRaw()) {
     case J:
-      Format(instr, "j       'imm26x");
+      Format(instr, "j       'imm26x -> 'imm26j");
       break;
     case JAL:
-      Format(instr, "jal     'imm26x");
+      Format(instr, "jal     'imm26x -> 'imm26j");
       break;
     default:
       UNREACHABLE();
   }
 }
 
 
 // Disassemble the instruction at *instr_ptr into the output buffer.
 int Decoder::InstructionDecode(byte* instr_ptr) {
   Instruction* instr = Instruction::At(instr_ptr);
@@ skipping 99 matching lines @@
         prev_pc, *reinterpret_cast<int32_t*>(prev_pc), buffer.start());
   }
 }
 
 
 #undef UNSUPPORTED
 
 }  // namespace disasm
 
 #endif  // V8_TARGET_ARCH_MIPS