Chromium Code Reviews
chromiumcodereview-hr@appspot.gserviceaccount.com (chromiumcodereview-hr) | Please choose your nickname with Settings | Help | Chromium Project | Gerrit Changes | Sign out
(118)

Issues Search
    My Issues | Starred     Open | Closed | All

Side by Side Diff: src/IceInstX8664.def

Issue 1212393005: Adds X8664 Condition codes. (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master
Patch Set: Created 5 years, 5 months ago
Use n/p to move between diff chunks; N/P to move between comments. Draft comments are only viewable by you.
Jump to:
View unified diff | Download patch
« no previous file with comments | « src/IceConditionCodesX8664.h ('k') | src/IceRegistersX8664.h » ('j') | no next file with comments »
Toggle Intra-line Diffs ('i') | Expand Comments ('e') | Collapse Comments ('c') | Show Comments Hide Comments ('s')
OLDNEW
1 //===- subzero/src/IceInstX8664.def - X-macros for x86-64 insts -*- C++ -*-===// 1 //===- subzero/src/IceInstX8664.def - X-macros for x86-64 insts -*- C++ -*-===//
2 // 2 //
3 // The Subzero Code Generator 3 // The Subzero Code Generator
4 // 4 //
5 // This file is distributed under the University of Illinois Open Source 5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details. 6 // License. See LICENSE.TXT for details.
7 // 7 //
8 //===----------------------------------------------------------------------===// 8 //===----------------------------------------------------------------------===//
9 // 9 //
10 // This file defines properties of lowered x86-64 instructions in the 10 // This file defines properties of lowered x86-64 instructions in the
(...skipping 21 matching lines...) Expand all
32 X(Reg_r10, = Reg_rax + 10, "r10", "r10d", "r10w", "r10l", 1, 0, 0, 0, 1, 0) \ 32 X(Reg_r10, = Reg_rax + 10, "r10", "r10d", "r10w", "r10l", 1, 0, 0, 0, 1, 0) \
33 X(Reg_r11, = Reg_rax + 11, "r11", "r11d", "r11w", "r11l", 1, 0, 0, 0, 1, 0) \ 33 X(Reg_r11, = Reg_rax + 11, "r11", "r11d", "r11w", "r11l", 1, 0, 0, 0, 1, 0) \
34 X(Reg_r12, = Reg_rax + 12, "r12", "r12d", "r12w", "r12l", 0, 1, 0, 0, 1, 0) \ 34 X(Reg_r12, = Reg_rax + 12, "r12", "r12d", "r12w", "r12l", 0, 1, 0, 0, 1, 0) \
35 X(Reg_r13, = Reg_rax + 13, "r13", "r13d", "r13w", "r12l", 0, 1, 0, 0, 1, 0) \ 35 X(Reg_r13, = Reg_rax + 13, "r13", "r13d", "r13w", "r12l", 0, 1, 0, 0, 1, 0) \
36 X(Reg_r14, = Reg_rax + 14, "r14", "r14d", "r14w", "r14l", 0, 1, 0, 0, 1, 0) \ 36 X(Reg_r14, = Reg_rax + 14, "r14", "r14d", "r14w", "r14l", 0, 1, 0, 0, 1, 0) \
37 X(Reg_r15, = Reg_rax + 15, "r15", "r15d", "r15w", "r15l", 0, 1, 0, 0, 1, 0) 37 X(Reg_r15, = Reg_rax + 15, "r15", "r15d", "r15w", "r15l", 0, 1, 0, 0, 1, 0)
38 38
39 #define REGX8664_XMM_TABLE \ 39 #define REGX8664_XMM_TABLE \
40 /* val, encode, name64, name, name16, name8, scratch, preserved, stackptr, \ 40 /* val, encode, name64, name, name16, name8, scratch, preserved, stackptr, \
41 frameptr, isInt, isFP */ \ 41 frameptr, isInt, isFP */ \
42 X(Reg_xmm0, = 0, "xmm0" , "", "", "", 1, 0, 0, 0, 0, 0, 1) \ 42 X(Reg_xmm0, = 0, "xmm0" , "", "", "", 1, 0, 0, 0, 0, 1) \
43 X(Reg_xmm1, = Reg_xmm0 + 1, "xmm1" , "", "", "", 1, 0, 0, 0, 0, 0, 1) \ 43 X(Reg_xmm1, = Reg_xmm0 + 1, "xmm1" , "", "", "", 1, 0, 0, 0, 0, 1) \
44 X(Reg_xmm2, = Reg_xmm0 + 2, "xmm2" , "", "", "", 1, 0, 0, 0, 0, 0, 1) \ 44 X(Reg_xmm2, = Reg_xmm0 + 2, "xmm2" , "", "", "", 1, 0, 0, 0, 0, 1) \
45 X(Reg_xmm3, = Reg_xmm0 + 3, "xmm3" , "", "", "", 1, 0, 0, 0, 0, 0, 1) \ 45 X(Reg_xmm3, = Reg_xmm0 + 3, "xmm3" , "", "", "", 1, 0, 0, 0, 0, 1) \
46 X(Reg_xmm4, = Reg_xmm0 + 4, "xmm4" , "", "", "", 1, 0, 0, 0, 0, 0, 1) \ 46 X(Reg_xmm4, = Reg_xmm0 + 4, "xmm4" , "", "", "", 1, 0, 0, 0, 0, 1) \
47 X(Reg_xmm5, = Reg_xmm0 + 5, "xmm5" , "", "", "", 1, 0, 0, 0, 0, 0, 1) \ 47 X(Reg_xmm5, = Reg_xmm0 + 5, "xmm5" , "", "", "", 1, 0, 0, 0, 0, 1) \
48 X(Reg_xmm6, = Reg_xmm0 + 6, "xmm6" , "", "", "", 1, 0, 0, 0, 0, 0, 1) \ 48 X(Reg_xmm6, = Reg_xmm0 + 6, "xmm6" , "", "", "", 1, 0, 0, 0, 0, 1) \
49 X(Reg_xmm7, = Reg_xmm0 + 7, "xmm7" , "", "", "", 1, 0, 0, 0, 0, 0, 1) \ 49 X(Reg_xmm7, = Reg_xmm0 + 7, "xmm7" , "", "", "", 1, 0, 0, 0, 0, 1) \
50 X(Reg_xmm8, = Reg_xmm0 + 8, "xmm8" , "", "", "", 1, 0, 0, 0, 0, 0, 1) \ 50 X(Reg_xmm8, = Reg_xmm0 + 8, "xmm8" , "", "", "", 1, 0, 0, 0, 0, 1) \
51 X(Reg_xmm9, = Reg_xmm0 + 9, "xmm9" , "", "", "", 1, 0, 0, 0, 0, 0, 1) \ 51 X(Reg_xmm9, = Reg_xmm0 + 9, "xmm9" , "", "", "", 1, 0, 0, 0, 0, 1) \
52 X(Reg_xmm10, = Reg_xmm0 + 10, "xmm10", "", "", "", 1, 0, 0, 0, 0, 0, 1) \ 52 X(Reg_xmm10, = Reg_xmm0 + 10, "xmm10", "", "", "", 1, 0, 0, 0, 0, 1) \
53 X(Reg_xmm11, = Reg_xmm0 + 11, "xmm11", "", "", "", 1, 0, 0, 0, 0, 0, 1) \ 53 X(Reg_xmm11, = Reg_xmm0 + 11, "xmm11", "", "", "", 1, 0, 0, 0, 0, 1) \
54 X(Reg_xmm12, = Reg_xmm0 + 12, "xmm12", "", "", "", 1, 0, 0, 0, 0, 0, 1) \ 54 X(Reg_xmm12, = Reg_xmm0 + 12, "xmm12", "", "", "", 1, 0, 0, 0, 0, 1) \
55 X(Reg_xmm13, = Reg_xmm0 + 13, "xmm13", "", "", "", 1, 0, 0, 0, 0, 0, 1) \ 55 X(Reg_xmm13, = Reg_xmm0 + 13, "xmm13", "", "", "", 1, 0, 0, 0, 0, 1) \
56 X(Reg_xmm14, = Reg_xmm0 + 14, "xmm14", "", "", "", 1, 0, 0, 0, 0, 0, 1) \ 56 X(Reg_xmm14, = Reg_xmm0 + 14, "xmm14", "", "", "", 1, 0, 0, 0, 0, 1) \
57 X(Reg_xmm15, = Reg_xmm0 + 15, "xmm15", "", "", "", 1, 0, 0, 0, 0, 0, 1) 57 X(Reg_xmm15, = Reg_xmm0 + 15, "xmm15", "", "", "", 1, 0, 0, 0, 0, 1)
58 //#define X(val, encode, name, name32, name16, name8, scratch, preserved, 58 //#define X(val, encode, name, name32, name16, name8, scratch, preserved,
59 // stackptr, frameptr, isI8, isInt, isFP) 59 // stackptr, frameptr, isI8, isInt, isFP)
60 60
61 // We also provide a combined table, so that there is a namespace where 61 // We also provide a combined table, so that there is a namespace where
62 // all of the registers are considered and have distinct numberings. 62 // all of the registers are considered and have distinct numberings.
63 // This is in contrast to the above, where the "encode" is based on how 63 // This is in contrast to the above, where the "encode" is based on how
64 // the register numbers will be encoded in binaries and values can overlap. 64 // the register numbers will be encoded in binaries and values can overlap.
65 // We don't want the register allocator choosing Reg_ah, in particular 65 // We don't want the register allocator choosing Reg_ah, in particular
66 // for lowering insertelement to pinsrb where internally we use an 66 // for lowering insertelement to pinsrb where internally we use an
67 // 8-bit operand but externally pinsrb uses a 32-bit register, in 67 // 8-bit operand but externally pinsrb uses a 32-bit register, in
(...skipping 13 matching lines...) Expand all
81 X(Reg_GPR_Last , = Reg_r15 ) \ 81 X(Reg_GPR_Last , = Reg_r15 ) \
82 X(Reg_XMM_First, = Reg_xmm0 ) \ 82 X(Reg_XMM_First, = Reg_xmm0 ) \
83 X(Reg_XMM_Last , = Reg_xmm15) 83 X(Reg_XMM_Last , = Reg_xmm15)
84 // define X(val, init) 84 // define X(val, init)
85 85
86 // We also need the encodings for the Byte registers (other info overlaps 86 // We also need the encodings for the Byte registers (other info overlaps
87 // what is in the REGX8664_GPR_TABLE). We don't expose the ah, ch, dh, 87 // what is in the REGX8664_GPR_TABLE). We don't expose the ah, ch, dh,
88 // bh registers to keep register selection simple. 88 // bh registers to keep register selection simple.
89 #define REGX8664_BYTEREG_TABLE \ 89 #define REGX8664_BYTEREG_TABLE \
90 /* val , encode */ \ 90 /* val , encode */ \
91 X(Reg_al , = 0) \ 91 X(Reg_al , = 0) \
92 X(Reg_cl , = Reg_al + 1) \ 92 X(Reg_cl , = 1) \
93 X(Reg_dl , = Reg_al + 2) \ 93 X(Reg_dl , = 2) \
94 X(Reg_bl , = Reg_al + 3) \ 94 X(Reg_bl , = 3) \
95 X(Reg_spl , = Reg_al + 4) \ 95 X(Reg_spl , = 4) \
96 X(Reg_bpl , = Reg_al + 5) \ 96 X(Reg_bpl , = 5) \
97 X(Reg_sil , = Reg_al + 6) \ 97 X(Reg_sil , = 6) \
98 X(Reg_dil , = Reg_al + 7) \ 98 X(Reg_dil , = 7) \
99 X(Reg_r8l , = Reg_al + 8) \ 99 X(Reg_r8l , = 8) \
100 X(Reg_r9l , = Reg_al + 9) \ 100 X(Reg_r9l , = 9) \
101 X(Reg_r10l, = Reg_al + 10) \ 101 X(Reg_r10l, = 10) \
102 X(Reg_r11l, = Reg_al + 11) \ 102 X(Reg_r11l, = 11) \
103 X(Reg_r12l, = Reg_al + 12) \ 103 X(Reg_r12l, = 12) \
104 X(Reg_r13l, = Reg_al + 13) \ 104 X(Reg_r13l, = 13) \
105 X(Reg_r14l, = Reg_al + 14) \ 105 X(Reg_r14l, = 14) \
106 X(Reg_r15l, = Reg_al + 15) 106 X(Reg_r15l, = 15)
107 //#define X(val, encode) 107 //#define X(val, encode)
108 108
109 #define ICEINSTX8664BR_TABLE \ 109 #define ICEINSTX8664BR_TABLE \
110 /* enum value, encode, opposite, dump, emit */ \ 110 /* enum value, encode, opposite, dump, emit */ \
111 X(Br_o , = 0, Br_no , "o" , "jo" ) \ 111 X(Br_o , = 0, Br_no , "o" , "jo" ) \
112 X(Br_no , = 1, Br_o , "no", "jno") \ 112 X(Br_no , = 1, Br_o , "no", "jno") \
113 X(Br_b , = 2, Br_ae , "b" , "jb" ) \ 113 X(Br_b , = 2, Br_ae , "b" , "jb" ) \
114 X(Br_ae , = 3, Br_b , "ae", "jae") \ 114 X(Br_ae , = 3, Br_b , "ae", "jae") \
115 X(Br_e , = 4, Br_ne , "e" , "je" ) \ 115 X(Br_e , = 4, Br_ne , "e" , "je" ) \
116 X(Br_ne , = 5, Br_e , "ne", "jne") \ 116 X(Br_ne , = 5, Br_e , "ne", "jne") \
117 X(Br_be , = 6, Br_a , "be", "jbe") \ 117 X(Br_be , = 6, Br_a , "be", "jbe") \
118 X(Br_a , = 7, Br_be , "a" , "ja" ) \ 118 X(Br_a , = 7, Br_be , "a" , "ja" ) \
119 X(Br_s , = 8, Br_ns , "s" , "js" ) \ 119 X(Br_s , = 8, Br_ns , "s" , "js" ) \
120 X(Br_ns , = 9, Br_s , "ns", "jns") \ 120 X(Br_ns , = 9, Br_s , "ns", "jns") \
121 X(Br_p , = 10, Br_np , "p" , "jp" ) \ 121 X(Br_p , = 10, Br_np , "p" , "jp" ) \
122 X(Br_np , = 11, Br_p , "np", "jnp") \ 122 X(Br_np , = 11, Br_p , "np", "jnp") \
123 X(Br_l , = 12, Br_ge , "l" , "jl" ) \ 123 X(Br_l , = 12, Br_ge , "l" , "jl" ) \
124 X(Br_ge , = 13, Br_l , "ge", "jge") \ 124 X(Br_ge , = 13, Br_l , "ge", "jge") \
125 X(Br_le , = 14, Br_g , "le", "jle") \ 125 X(Br_le , = 14, Br_g , "le", "jle") \
126 X(Br_g , = 15, Br_le , "g" , "jg"): 126 X(Br_g , = 15, Br_le , "g" , "jg")
127 //#define X(tag, encode, opp, dump, emit) 127 //#define X(tag, encode, opp, dump, emit)
128 128
129 #define ICEINSTX8664CMPPS_TABLE \ 129 #define ICEINSTX8664CMPPS_TABLE \
130 /* enum value, emit */ \ 130 /* enum value, emit */ \
131 X(Cmpps_eq , "eq" ) \ 131 X(Cmpps_eq , "eq" ) \
132 X(Cmpps_lt , "lt" ) \ 132 X(Cmpps_lt , "lt" ) \
133 X(Cmpps_le , "le" ) \ 133 X(Cmpps_le , "le" ) \
134 X(Cmpps_unord, "unord") \ 134 X(Cmpps_unord, "unord") \
135 X(Cmpps_neq , "neq" ) \ 135 X(Cmpps_neq , "neq" ) \
136 X(Cmpps_nlt , "nlt" ) \ 136 X(Cmpps_nlt , "nlt" ) \
(...skipping 14 matching lines...) Expand all
151 X(IceType_v4i1 , IceType_i32 , "?" , "" , "d" , "" , "" ) \ 151 X(IceType_v4i1 , IceType_i32 , "?" , "" , "d" , "" , "" ) \
152 X(IceType_v8i1 , IceType_i16 , "?" , "" , "w" , "" , "" ) \ 152 X(IceType_v8i1 , IceType_i16 , "?" , "" , "w" , "" , "" ) \
153 X(IceType_v16i1, IceType_i8 , "?" , "" , "b" , "" , "" ) \ 153 X(IceType_v16i1, IceType_i8 , "?" , "" , "b" , "" , "" ) \
154 X(IceType_v16i8, IceType_i8 , "?" , "" , "b" , "" , "" ) \ 154 X(IceType_v16i8, IceType_i8 , "?" , "" , "b" , "" , "" ) \
155 X(IceType_v8i16, IceType_i16 , "?" , "" , "w" , "" , "" ) \ 155 X(IceType_v8i16, IceType_i16 , "?" , "" , "w" , "" , "" ) \
156 X(IceType_v4i32, IceType_i32 , "dq", "" , "d" , "" , "" ) \ 156 X(IceType_v4i32, IceType_i32 , "dq", "" , "d" , "" , "" ) \
157 X(IceType_v4f32, IceType_f32 , "ps", "" , "d" , "" , "" ) 157 X(IceType_v4f32, IceType_f32 , "ps", "" , "d" , "" , "" )
158 //#define X(tag, elementty, cvt, sdss, pack, width, fld) 158 //#define X(tag, elementty, cvt, sdss, pack, width, fld)
159 159
160 #endif // SUBZERO_SRC_ICEINSTX8664_DEF 160 #endif // SUBZERO_SRC_ICEINSTX8664_DEF
OLDNEW
« no previous file with comments | « src/IceConditionCodesX8664.h ('k') | src/IceRegistersX8664.h » ('j') | no next file with comments »

Powered by Google App Engine
This is Rietveld 408576698