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1 // Copyright (c) 2006-2008 The Chromium Authors. All rights reserved. | |
2 // Use of this source code is governed by a BSD-style license that can be | |
3 // found in the LICENSE file. | |
4 | |
5 // This module gets enough CPU information to optimize the | |
6 // atomicops module on x86. | |
7 | |
8 #include <stdint.h> | |
9 #include <string.h> | |
10 | |
11 #include "base/atomicops.h" | |
12 | |
13 // Inline cpuid instruction. In PIC compilations, %ebx contains the address | |
14 // of the global offset table. To avoid breaking such executables, this code | |
15 // must preserve that register's value across cpuid instructions. | |
16 // | |
17 // The include guards are the same as in atomicops.h. | |
18 #if defined(__i386__) | |
19 #define cpuid(a, b, c, d, inp) \ | |
20 asm("mov %%ebx, %%edi\n" \ | |
21 "cpuid\n" \ | |
22 "xchg %%edi, %%ebx\n" \ | |
23 : "=a" (a), "=D" (b), "=c" (c), "=d" (d) : "a" (inp)) | |
24 #elif defined(__x86_64__) | |
25 #define cpuid(a, b, c, d, inp) \ | |
26 asm("mov %%rbx, %%rdi\n" \ | |
27 "cpuid\n" \ | |
28 "xchg %%rdi, %%rbx\n" \ | |
29 : "=a" (a), "=D" (b), "=c" (c), "=d" (d) : "a" (inp)) | |
30 #endif | |
31 | |
32 #if defined(cpuid) // initialize the struct only on x86 | |
33 | |
34 // Set the flags so that code will run correctly and conservatively, so even | |
35 // if we haven't been initialized yet, we're probably single threaded, and our | |
36 // default values should hopefully be pretty safe. | |
37 struct AtomicOps_x86CPUFeatureStruct AtomicOps_Internalx86CPUFeatures = { | |
38 false, // bug can't exist before process spawns multiple threads | |
39 false, // Chrome requires SSE2, but for transition assume not and initialize | |
40 // this properly. | |
41 false, // cmpxchg16b isn't present on early AMD64 CPUs. | |
42 }; | |
43 | |
44 namespace { | |
45 | |
46 // Initialize the AtomicOps_Internalx86CPUFeatures struct. | |
47 void AtomicOps_Internalx86CPUFeaturesInit() { | |
48 uint32_t eax; | |
49 uint32_t ebx; | |
50 uint32_t ecx; | |
51 uint32_t edx; | |
52 | |
53 // Get vendor string (issue CPUID with eax = 0) | |
54 cpuid(eax, ebx, ecx, edx, 0); | |
55 char vendor[13]; | |
56 memcpy(vendor, &ebx, 4); | |
57 memcpy(vendor + 4, &edx, 4); | |
58 memcpy(vendor + 8, &ecx, 4); | |
59 vendor[12] = 0; | |
60 | |
61 // get feature flags in ecx/edx, and family/model in eax | |
62 cpuid(eax, ebx, ecx, edx, 1); | |
63 | |
64 int family = (eax >> 8) & 0xf; // family and model fields | |
65 int model = (eax >> 4) & 0xf; | |
66 if (family == 0xf) { // use extended family and model fields | |
67 family += (eax >> 20) & 0xff; | |
68 model += ((eax >> 16) & 0xf) << 4; | |
69 } | |
70 | |
71 // Opteron Rev E has a bug in which on very rare occasions a locked | |
72 // instruction doesn't act as a read-acquire barrier if followed by a | |
73 // non-locked read-modify-write instruction. Rev F has this bug in | |
74 // pre-release versions, but not in versions released to customers, | |
75 // so we test only for Rev E, which is family 15, model 32..63 inclusive. | |
76 if (strcmp(vendor, "AuthenticAMD") == 0 && // AMD | |
77 family == 15 && | |
78 32 <= model && model <= 63) { | |
79 AtomicOps_Internalx86CPUFeatures.has_amd_lock_mb_bug = true; | |
80 } else { | |
81 AtomicOps_Internalx86CPUFeatures.has_amd_lock_mb_bug = false; | |
82 } | |
83 | |
84 // edx bit 26 is SSE2 which we use to tell use whether we can use mfence | |
85 AtomicOps_Internalx86CPUFeatures.has_sse2 = ((edx >> 26) & 1); | |
86 | |
87 // ecx bit 13 indicates whether the cmpxchg16b instruction is supported | |
88 AtomicOps_Internalx86CPUFeatures.has_cmpxchg16b = ((ecx >> 13) & 1); | |
89 } | |
90 | |
91 class AtomicOpsx86Initializer { | |
92 public: | |
93 AtomicOpsx86Initializer() { | |
94 AtomicOps_Internalx86CPUFeaturesInit(); | |
95 } | |
96 }; | |
97 | |
98 // A global to get use initialized on startup via static initialization :/ | |
99 AtomicOpsx86Initializer g_initer; | |
100 | |
101 } // namespace | |
102 | |
103 #endif // if x86 | |
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