ARM: lowerSelect for integers.

src/IceTargetLoweringARM32.cpp

 //===- subzero/src/IceTargetLoweringARM32.cpp - ARM32 lowering ------------===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file implements the TargetLoweringARM32 class, which consists almost
@@ skipping 1991 matching lines @@
   // Add a fake use of sp to make sure sp stays alive for the entire
   // function.  Otherwise post-call sp adjustments get dead-code
   // eliminated.  TODO: Are there more places where the fake use
   // should be inserted?  E.g. "void f(int n){while(1) g(n);}" may not
   // have a ret instruction.
   Variable *SP = Func->getTarget()->getPhysicalRegister(RegARM32::Reg_sp);
   Context.insert(InstFakeUse::create(Func, SP));
 }
 
 void TargetARM32::lowerSelect(const InstSelect *Inst) {
-  (void)Inst;
-  UnimplementedError(Func->getContext()->getFlags());
+  Variable *Dest = Inst->getDest();
+  Type DestTy = Dest->getType();
+  Operand *SrcT = Inst->getTrueOperand();
+  Operand *SrcF = Inst->getFalseOperand();
+  Operand *Condition = Inst->getCondition();
+
+  if (isVectorType(DestTy)) {
+    UnimplementedError(Func->getContext()->getFlags());
+    return;
+  }
+  if (isFloatingType(DestTy)) {
+    UnimplementedError(Func->getContext()->getFlags());
+    return;
+  }
+  // TODO(jvoung): handle folding opportunities.
+  // cmp cond, #0; mov t, SrcF; mov_cond t, SrcT; mov dest, t
+  Variable *CmpOpnd0 = legalizeToVar(Condition);
+  Operand *CmpOpnd1 = Ctx->getConstantZero(IceType_i32);
+  _cmp(CmpOpnd0, CmpOpnd1);
+  CondARM32::Cond Cond = CondARM32::NE;
+  if (DestTy == IceType_i64) {
+    // Set the low portion.
+    Variable *DestLo = llvm::cast<Variable>(loOperand(Dest));
+    Variable *TLo = nullptr;
+    Operand *SrcFLo = legalize(loOperand(SrcF), Legal_Reg | Legal_Flex);
+    _mov(TLo, SrcFLo);
+    Operand *SrcTLo = legalize(loOperand(SrcT), Legal_Reg | Legal_Flex);
+    _mov_nonkillable(TLo, SrcTLo, Cond);
+    _mov(DestLo, TLo);
+    // Set the high portion.
+    Variable *DestHi = llvm::cast<Variable>(hiOperand(Dest));
+    Variable *THi = nullptr;
+    Operand *SrcFHi = legalize(hiOperand(SrcF), Legal_Reg | Legal_Flex);
+    _mov(THi, SrcFHi);
+    Operand *SrcTHi = legalize(hiOperand(SrcT), Legal_Reg | Legal_Flex);
+    _mov_nonkillable(THi, SrcTHi, Cond);
+    _mov(DestHi, THi);
+    return;
+  }
+  Variable *T = nullptr;
+  SrcF = legalize(SrcF, Legal_Reg | Legal_Flex);
+  _mov(T, SrcF);
+  SrcT = legalize(SrcT, Legal_Reg | Legal_Flex);
+  _mov_nonkillable(T, SrcT, Cond);
+  _mov(Dest, T);
 }
 
 void TargetARM32::lowerStore(const InstStore *Inst) {
   Operand *Value = Inst->getData();
   Operand *Addr = Inst->getAddr();
   OperandARM32Mem *NewAddr = formMemoryOperand(Addr, Value->getType());
   Type Ty = NewAddr->getType();
 
   if (Ty == IceType_i64) {
     Variable *ValueHi = legalizeToVar(hiOperand(Value));
@@ skipping 26 matching lines @@
       Operand *ValueHi = Ctx->getConstantInt32(Inst->getValue(I) >> 32);
       ValueLo = legalize(ValueLo, Legal_Reg | Legal_Flex);
       ValueHi = legalize(ValueHi, Legal_Reg | Legal_Flex);
       _cmp(Src0Lo, ValueLo);
       _cmp(Src0Hi, ValueHi, CondARM32::EQ);
       _br(Inst->getLabel(I), CondARM32::EQ);
     }
     _br(Inst->getLabelDefault());
     return;
   }
- 
+
   // 32 bit integer
   Variable *Src0Var = legalizeToVar(Src0);
   for (SizeT I = 0; I < NumCases; ++I) {
     Operand *Value = Ctx->getConstantInt32(Inst->getValue(I));
     Value = legalize(Value, Legal_Reg | Legal_Flex);
     _cmp(Src0Var, Value);
     _br(Inst->getLabel(I), CondARM32::EQ);
   }
   _br(Inst->getLabelDefault());
 }
@@ skipping 335 matching lines @@
       << ".eabi_attribute 36, 1   @ Tag_FP_HP_extension\n"
       << ".eabi_attribute 38, 1   @ Tag_ABI_FP_16bit_format\n"
       << ".eabi_attribute 42, 1   @ Tag_MPextension_use\n"
       << ".eabi_attribute 68, 1   @ Tag_Virtualization_use\n";
   // Technically R9 is used for TLS with Sandboxing, and we reserve it.
   // However, for compatibility with current NaCl LLVM, don't claim that.
   Str << ".eabi_attribute 14, 3   @ Tag_ABI_PCS_R9_use: Not used\n";
 }
 
 } // end of namespace Ice