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| 1 //===- subzero/src/IceInstX8664.def - X-macros for x86-64 insts -*- C++ -*-===// |
| 2 // |
| 3 // The Subzero Code Generator |
| 4 // |
| 5 // This file is distributed under the University of Illinois Open Source |
| 6 // License. See LICENSE.TXT for details. |
| 7 // |
| 8 //===----------------------------------------------------------------------===// |
| 9 // |
| 10 // This file defines properties of lowered x86-64 instructions in the |
| 11 // form of x-macros. |
| 12 // |
| 13 //===----------------------------------------------------------------------===// |
| 14 |
| 15 #ifndef SUBZERO_SRC_ICEINSTX8664_DEF |
| 16 #define SUBZERO_SRC_ICEINSTX8664_DEF |
| 17 |
| 18 // NOTE: esp is not considered isInt, to avoid register allocating it. |
| 19 #define REGX8664_GPR_TABLE \ |
| 20 /* val, encode, name64, name, name16, name8, scratch, preserved, stackptr, \ |
| 21 frameptr, isInt, isFP */ \ |
| 22 X(Reg_rax, = 0, "rax", "eax" , "ax" , "al" , 1, 0, 0, 0, 1, 0) \ |
| 23 X(Reg_rcx, = Reg_rax + 1, "rcx", "ecx" , "cx" , "cl" , 1, 0, 0, 0, 1, 0) \ |
| 24 X(Reg_rdx, = Reg_rax + 2, "rdx", "edx" , "dx" , "dl" , 1, 0, 0, 0, 1, 0) \ |
| 25 X(Reg_rbx, = Reg_rax + 3, "rbx", "ebx" , "bx" , "bl" , 0, 1, 0, 0, 1, 0) \ |
| 26 X(Reg_rsp, = Reg_rax + 4, "rsp", "esp" , "sp" , "spl" , 0, 0, 1, 0, 0, 0) \ |
| 27 X(Reg_rbp, = Reg_rax + 5, "rbp", "ebp" , "bp" , "bpl" , 0, 0, 0, 1, 1, 0) \ |
| 28 X(Reg_rsi, = Reg_rax + 6, "rsi", "esi" , "si" , "sil" , 1, 0, 0, 0, 1, 0) \ |
| 29 X(Reg_rdi, = Reg_rax + 7, "rdi", "edi" , "di" , "dil" , 1, 0, 0, 0, 1, 0) \ |
| 30 X(Reg_r8, = Reg_rax + 8, "r8" , "r8d" , "r8w", "r8l" , 1, 0, 0, 0, 1, 0) \ |
| 31 X(Reg_r9, = Reg_rax + 9, "r9" , "r9d" , "r9w", "r9l" , 1, 0, 0, 0, 1, 0) \ |
| 32 X(Reg_r10, = Reg_rax + 10, "r10", "r10d", "r10w", "r10l", 1, 0, 0, 0, 1, 0) \ |
| 33 X(Reg_r11, = Reg_rax + 11, "r11", "r11d", "r11w", "r11l", 1, 0, 0, 0, 1, 0) \ |
| 34 X(Reg_r12, = Reg_rax + 12, "r12", "r12d", "r12w", "r12l", 0, 1, 0, 0, 1, 0) \ |
| 35 X(Reg_r13, = Reg_rax + 13, "r13", "r13d", "r13w", "r12l", 0, 1, 0, 0, 1, 0) \ |
| 36 X(Reg_r14, = Reg_rax + 14, "r14", "r14d", "r14w", "r14l", 0, 1, 0, 0, 1, 0) \ |
| 37 X(Reg_r15, = Reg_rax + 15, "r15", "r15d", "r15w", "r15l", 0, 1, 0, 0, 1, 0) |
| 38 |
| 39 #define REGX8664_XMM_TABLE \ |
| 40 /* val, encode, name64, name, name16, name8, scratch, preserved, stackptr, \ |
| 41 frameptr, isInt, isFP */ \ |
| 42 X(Reg_xmm0, = 0, "xmm0" , "", "", "", 1, 0, 0, 0, 0, 0, 1) \ |
| 43 X(Reg_xmm1, = Reg_xmm0 + 1, "xmm1" , "", "", "", 1, 0, 0, 0, 0, 0, 1) \ |
| 44 X(Reg_xmm2, = Reg_xmm0 + 2, "xmm2" , "", "", "", 1, 0, 0, 0, 0, 0, 1) \ |
| 45 X(Reg_xmm3, = Reg_xmm0 + 3, "xmm3" , "", "", "", 1, 0, 0, 0, 0, 0, 1) \ |
| 46 X(Reg_xmm4, = Reg_xmm0 + 4, "xmm4" , "", "", "", 1, 0, 0, 0, 0, 0, 1) \ |
| 47 X(Reg_xmm5, = Reg_xmm0 + 5, "xmm5" , "", "", "", 1, 0, 0, 0, 0, 0, 1) \ |
| 48 X(Reg_xmm6, = Reg_xmm0 + 6, "xmm6" , "", "", "", 1, 0, 0, 0, 0, 0, 1) \ |
| 49 X(Reg_xmm7, = Reg_xmm0 + 7, "xmm7" , "", "", "", 1, 0, 0, 0, 0, 0, 1) \ |
| 50 X(Reg_xmm8, = Reg_xmm0 + 8, "xmm8" , "", "", "", 1, 0, 0, 0, 0, 0, 1) \ |
| 51 X(Reg_xmm9, = Reg_xmm0 + 9, "xmm9" , "", "", "", 1, 0, 0, 0, 0, 0, 1) \ |
| 52 X(Reg_xmm10, = Reg_xmm0 + 10, "xmm10", "", "", "", 1, 0, 0, 0, 0, 0, 1) \ |
| 53 X(Reg_xmm11, = Reg_xmm0 + 11, "xmm11", "", "", "", 1, 0, 0, 0, 0, 0, 1) \ |
| 54 X(Reg_xmm12, = Reg_xmm0 + 12, "xmm12", "", "", "", 1, 0, 0, 0, 0, 0, 1) \ |
| 55 X(Reg_xmm13, = Reg_xmm0 + 13, "xmm13", "", "", "", 1, 0, 0, 0, 0, 0, 1) \ |
| 56 X(Reg_xmm14, = Reg_xmm0 + 14, "xmm14", "", "", "", 1, 0, 0, 0, 0, 0, 1) \ |
| 57 X(Reg_xmm15, = Reg_xmm0 + 15, "xmm15", "", "", "", 1, 0, 0, 0, 0, 0, 1) |
| 58 //#define X(val, encode, name, name32, name16, name8, scratch, preserved, |
| 59 // stackptr, frameptr, isI8, isInt, isFP) |
| 60 |
| 61 // We also provide a combined table, so that there is a namespace where |
| 62 // all of the registers are considered and have distinct numberings. |
| 63 // This is in contrast to the above, where the "encode" is based on how |
| 64 // the register numbers will be encoded in binaries and values can overlap. |
| 65 // We don't want the register allocator choosing Reg_ah, in particular |
| 66 // for lowering insertelement to pinsrb where internally we use an |
| 67 // 8-bit operand but externally pinsrb uses a 32-bit register, in |
| 68 // which Reg_ah doesn't map to eax. |
| 69 #define REGX8664_TABLE \ |
| 70 /* val, encode, name64, name, name16, name8, scratch, preserved, \ |
| 71 stackptr, frameptr, isInt, isFP */ \ |
| 72 REGX8664_GPR_TABLE \ |
| 73 X(Reg_ah, = Reg_rax + 4, "?ah", "?ah", "?ah", "ah", 0, 0, 0, 0, 0, 0) \ |
| 74 REGX8664_XMM_TABLE |
| 75 //#define X(val, encode, name, name32, name16, name8, scratch, preserved, |
| 76 // stackptr, frameptr, isI8, isInt, isFP) |
| 77 |
| 78 #define REGX8664_TABLE_BOUNDS \ |
| 79 /* val , init */ \ |
| 80 X(Reg_GPR_First, = Reg_rax ) \ |
| 81 X(Reg_GPR_Last , = Reg_r15 ) \ |
| 82 X(Reg_XMM_First, = Reg_xmm0 ) \ |
| 83 X(Reg_XMM_Last , = Reg_xmm15) |
| 84 // define X(val, init) |
| 85 |
| 86 // We also need the encodings for the Byte registers (other info overlaps |
| 87 // what is in the REGX8664_GPR_TABLE). We don't expose the ah, ch, dh, |
| 88 // bh registers to keep register selection simple. |
| 89 #define REGX8664_BYTEREG_TABLE \ |
| 90 /* val , encode */ \ |
| 91 X(Reg_al , = 0) \ |
| 92 X(Reg_cl , = Reg_al + 1) \ |
| 93 X(Reg_dl , = Reg_al + 2) \ |
| 94 X(Reg_bl , = Reg_al + 3) \ |
| 95 X(Reg_spl , = Reg_al + 4) \ |
| 96 X(Reg_bpl , = Reg_al + 5) \ |
| 97 X(Reg_sil , = Reg_al + 6) \ |
| 98 X(Reg_dil , = Reg_al + 7) \ |
| 99 X(Reg_r8l , = Reg_al + 8) \ |
| 100 X(Reg_r9l , = Reg_al + 9) \ |
| 101 X(Reg_r10l, = Reg_al + 10) \ |
| 102 X(Reg_r11l, = Reg_al + 11) \ |
| 103 X(Reg_r12l, = Reg_al + 12) \ |
| 104 X(Reg_r13l, = Reg_al + 13) \ |
| 105 X(Reg_r14l, = Reg_al + 14) \ |
| 106 X(Reg_r15l, = Reg_al + 15) |
| 107 //#define X(val, encode) |
| 108 |
| 109 #define ICEINSTX8664BR_TABLE \ |
| 110 /* enum value, encode, opposite, dump, emit */ \ |
| 111 X(Br_o , = 0, Br_no , "o" , "jo" ) \ |
| 112 X(Br_no , = 1, Br_o , "no", "jno") \ |
| 113 X(Br_b , = 2, Br_ae , "b" , "jb" ) \ |
| 114 X(Br_ae , = 3, Br_b , "ae", "jae") \ |
| 115 X(Br_e , = 4, Br_ne , "e" , "je" ) \ |
| 116 X(Br_ne , = 5, Br_e , "ne", "jne") \ |
| 117 X(Br_be , = 6, Br_a , "be", "jbe") \ |
| 118 X(Br_a , = 7, Br_be , "a" , "ja" ) \ |
| 119 X(Br_s , = 8, Br_ns , "s" , "js" ) \ |
| 120 X(Br_ns , = 9, Br_s , "ns", "jns") \ |
| 121 X(Br_p , = 10, Br_np , "p" , "jp" ) \ |
| 122 X(Br_np , = 11, Br_p , "np", "jnp") \ |
| 123 X(Br_l , = 12, Br_ge , "l" , "jl" ) \ |
| 124 X(Br_ge , = 13, Br_l , "ge", "jge") \ |
| 125 X(Br_le , = 14, Br_g , "le", "jle") \ |
| 126 X(Br_g , = 15, Br_le , "g" , "jg"): |
| 127 //#define X(tag, encode, opp, dump, emit) |
| 128 |
| 129 #define ICEINSTX8664CMPPS_TABLE \ |
| 130 /* enum value, emit */ \ |
| 131 X(Cmpps_eq , "eq" ) \ |
| 132 X(Cmpps_lt , "lt" ) \ |
| 133 X(Cmpps_le , "le" ) \ |
| 134 X(Cmpps_unord, "unord") \ |
| 135 X(Cmpps_neq , "neq" ) \ |
| 136 X(Cmpps_nlt , "nlt" ) \ |
| 137 X(Cmpps_nle , "nle" ) \ |
| 138 X(Cmpps_ord , "ord" ) |
| 139 //#define X(tag, emit) |
| 140 |
| 141 #define ICETYPEX8664_TABLE \ |
| 142 /* tag , element type, cvt , sdss, pack, width, fld */ \ |
| 143 X(IceType_void , IceType_void, "?" , "" , "" , "" , "" ) \ |
| 144 X(IceType_i1 , IceType_void, "si", "" , "" , "b" , "" ) \ |
| 145 X(IceType_i8 , IceType_void, "si", "" , "" , "b" , "" ) \ |
| 146 X(IceType_i16 , IceType_void, "si", "" , "" , "w" , "" ) \ |
| 147 X(IceType_i32 , IceType_void, "si", "" , "" , "l" , "" ) \ |
| 148 X(IceType_i64 , IceType_void, "si", "" , "" , "q" , "" ) \ |
| 149 X(IceType_f32 , IceType_void, "ss", "ss", "d" , "" , "s") \ |
| 150 X(IceType_f64 , IceType_void, "sd", "sd", "q" , "" , "l") \ |
| 151 X(IceType_v4i1 , IceType_i32 , "?" , "" , "d" , "" , "" ) \ |
| 152 X(IceType_v8i1 , IceType_i16 , "?" , "" , "w" , "" , "" ) \ |
| 153 X(IceType_v16i1, IceType_i8 , "?" , "" , "b" , "" , "" ) \ |
| 154 X(IceType_v16i8, IceType_i8 , "?" , "" , "b" , "" , "" ) \ |
| 155 X(IceType_v8i16, IceType_i16 , "?" , "" , "w" , "" , "" ) \ |
| 156 X(IceType_v4i32, IceType_i32 , "dq", "" , "d" , "" , "" ) \ |
| 157 X(IceType_v4f32, IceType_f32 , "ps", "" , "d" , "" , "" ) |
| 158 //#define X(tag, elementty, cvt, sdss, pack, width, fld) |
| 159 |
| 160 #endif // SUBZERO_SRC_ICEINSTX8664_DEF |
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Chromium Code Reviews
Issue 1211103004:
Adds the X8664 register definition. (Closed)
Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master