Subzero: Avoid unused insts for ARM Om1 lowering for arithmetic

tests_lit/llvm2ice_tests/64bit.pnacl.ll

 ; This tries to be a comprehensive test of i64 operations, in
 ; particular the patterns for lowering i64 operations into constituent
 ; i32 operations on x86-32.
 
 ; RUN: %if --need=target_X8632 --command %p2i --filetype=obj --disassemble \
 ; RUN:   --target x8632 -i %s --args -O2 \
 ; RUN:   | %if --need=target_X8632 --command FileCheck %s
 
 ; RUN: %if --need=target_X8632 --command %p2i --filetype=obj --disassemble \
 ; RUN:   --target x8632 -i %s --args -Om1 \
 ; RUN:   | %if --need=target_X8632 --command FileCheck --check-prefix=OPTM1 %s
 
 ; TODO(jvoung): Stop skipping unimplemented parts (via --skip-unimplemented)
 ; once enough infrastructure is in. Also, switch to --filetype=obj
 ; when possible.
 ; RUN: %if --need=target_ARM32 --need=allow_dump \
 ; RUN:   --command %p2i --filetype=asm --assemble \
 ; RUN:   --disassemble --target arm32 -i %s --args -O2 --skip-unimplemented \
 ; RUN:   | %if --need=target_ARM32 --need=allow_dump \
 ; RUN:   --command FileCheck --check-prefix ARM32 %s
+; RUN: %if --need=target_ARM32 --need=allow_dump \
+; RUN:   --command %p2i --filetype=asm --assemble --disassemble --target arm32 \
+; RUN:   -i %s --args -Om1 --skip-unimplemented \
+; RUN:   | %if --need=target_ARM32 --need=allow_dump \
+; RUN:   --command FileCheck --check-prefix ARM32 %s
 
 @__init_array_start = internal constant [0 x i8] zeroinitializer, align 4
 @__fini_array_start = internal constant [0 x i8] zeroinitializer, align 4
 @__tls_template_start = internal constant [0 x i8] zeroinitializer, align 8
 @__tls_template_alignment = internal constant [4 x i8] c"\01\00\00\00", align 4
 
 define internal i32 @ignore64BitArg(i64 %a, i32 %b, i64 %c) {
 entry:
   ret i32 %b
 }
@@ skipping 56 matching lines @@
 ; ARM32-LABEL: pass64BitArg
 ; ARM32:      sub     sp, {{.*}} #16
 ; ARM32:      str     {{.*}}, [sp, #4]
 ; ARM32:      str     {{.*}}, [sp]
 ; ARM32:      movw    r2, #123
 ; ARM32:      bl      {{.*}} ignore64BitArgNoInline
 ; ARM32:      add     sp, {{.*}} #16
 ; ARM32:      sub     sp, {{.*}} #16
 ; ARM32:      str     {{.*}}, [sp, #4]
 ; ARM32:      str     {{.*}}, [sp]
-; ARM32:      mov     r0
-; ARM32:      mov     r1
+; ARM32:      {{mov|ldr}} r0
+; ARM32:      {{mov|ldr}} r1
 ; ARM32:      movw    r2, #123
 ; ARM32:      bl      {{.*}} ignore64BitArgNoInline
 ; ARM32:      add     sp, {{.*}} #16
 ; ARM32:      sub     sp, {{.*}} #16
 ; ARM32:      str     {{.*}}, [sp, #4]
 ; ARM32:      str     {{.*}}, [sp]
-; ARM32:      mov     r0
-; ARM32:      mov     r1
+; ARM32:      {{mov|ldr}} r0
+; ARM32:      {{mov|ldr}} r1
 ; ARM32:      movw    r2, #123
 ; ARM32:      bl      {{.*}} ignore64BitArgNoInline
 ; ARM32:      add     sp, {{.*}} #16
 
 
 declare i32 @ignore64BitArgNoInline(i64, i32, i64)
 
 define internal i32 @pass64BitConstArg(i64 %a, i64 %b) {
 entry:
   %call = call i32 @ignore64BitArgNoInline(i64 %b, i32 123, i64 -2401053092306725256)
@@ skipping 23 matching lines @@
 ; OPTM1:      call {{.*}} R_{{.*}}    ignore64BitArgNoInline
 
 ; ARM32-LABEL: pass64BitConstArg
 ; ARM32:      sub     sp, {{.*}} #16
 ; ARM32:      movw    [[REG1:r.*]], {{.*}} ; 0xbeef
 ; ARM32:      movt    [[REG1:r.*]], {{.*}} ; 0xdead
 ; ARM32:      movw    [[REG2:r.*]], {{.*}} ; 0x5678
 ; ARM32:      movt    [[REG2:r.*]], {{.*}} ; 0x1234
 ; ARM32:      str     [[REG1]], [sp, #4]
 ; ARM32:      str     [[REG2]], [sp]
-; ARM32:      mov     r0, r2
-; ARM32:      mov     r1, r3
+; ARM32:      {{mov|ldr}} r0
+; ARM32:      {{mov|ldr}} r1
 ; ARM32:      movw    r2, #123
 ; ARM32:      bl      {{.*}} ignore64BitArgNoInline
 ; ARM32:      add     sp, {{.*}} #16
 
-define internal i64 @return64BitArg(i64 %a) {
+define internal i64 @return64BitArg(i64 %padding, i64 %a) {
 entry:
   ret i64 %a
 }
 ; CHECK-LABEL: return64BitArg
-; CHECK: mov     {{.*}},DWORD PTR [esp+0x4]
-; CHECK: mov     {{.*}},DWORD PTR [esp+0x8]
+; CHECK: mov     {{.*}},DWORD PTR [esp+0xc]
+; CHECK: mov     {{.*}},DWORD PTR [esp+0x10]
 ;
 ; OPTM1-LABEL: return64BitArg
-; OPTM1: mov     {{.*}},DWORD PTR [esp+0x4]
-; OPTM1: mov     {{.*}},DWORD PTR [esp+0x8]
+; OPTM1: mov     {{.*}},DWORD PTR [esp+0xc]
+; OPTM1: mov     {{.*}},DWORD PTR [esp+0x10]
 
-; Nothing to do for ARM O2 -- arg and return value are in r0,r1.
 ; ARM32-LABEL: return64BitArg
-; ARM32-NEXT: bx lr
+; ARM32: mov {{.*}}, r2
+; ARM32: mov {{.*}}, r3
+; ARM32: bx lr
 
 define internal i64 @return64BitConst() {
 entry:
   ret i64 -2401053092306725256
 }
 ; CHECK-LABEL: return64BitConst
 ; CHECK: mov     eax,0x12345678
 ; CHECK: mov     edx,0xdeadbeef
 ;
 ; OPTM1-LABEL: return64BitConst
@@ skipping 814 matching lines @@
 ; OPTM1: call
 ; OPTM1: jne
 ; OPTM1: je
 ; OPTM1: call
 
 ; ARM32-LABEL: icmpEq64
 ; ARM32: cmp
 ; ARM32: cmpeq
 ; ARM32: moveq
 ; ARM32: movne
-; ARM32: beq
 ; ARM32: bl
 ; ARM32: cmp
 ; ARM32: cmpeq
 ; ARM32: moveq
 ; ARM32: movne
-; ARM32: beq
 ; ARM32: bl
 
 declare void @func()
 
 define internal void @icmpNe64(i64 %a, i64 %b, i64 %c, i64 %d) {
 entry:
   %cmp = icmp ne i64 %a, %b
   br i1 %cmp, label %if.then, label %if.end
 
 if.then:                                          ; preds = %entry
@@ skipping 25 matching lines @@
 ; OPTM1: call
 ; OPTM1: jne
 ; OPTM1: jne
 ; OPTM1: call
 
 ; ARM32-LABEL: icmpNe64
 ; ARM32: cmp
 ; ARM32: cmpeq
 ; ARM32: movne
 ; ARM32: moveq
-; ARM32: beq
 ; ARM32: bl
 ; ARM32: cmp
 ; ARM32: cmpeq
 ; ARM32: movne
 ; ARM32: moveq
-; ARM32: beq
 ; ARM32: bl
 
 define internal void @icmpGt64(i64 %a, i64 %b, i64 %c, i64 %d) {
 entry:
   %cmp = icmp ugt i64 %a, %b
   br i1 %cmp, label %if.then, label %if.end
 
 if.then:                                          ; preds = %entry
   call void @func()
   br label %if.end
@@ skipping 27 matching lines @@
 ; OPTM1: jg
 ; OPTM1: jl
 ; OPTM1: ja
 ; OPTM1: call
 
 ; ARM32-LABEL: icmpGt64
 ; ARM32: cmp
 ; ARM32: cmpeq
 ; ARM32: movhi
 ; ARM32: movls
-; ARM32: beq
 ; ARM32: bl
 ; ARM32: cmp
 ; ARM32: sbcs
 ; ARM32: movlt
 ; ARM32: movge
-; ARM32: beq
 ; ARM32: bl
 
 define internal void @icmpGe64(i64 %a, i64 %b, i64 %c, i64 %d) {
 entry:
   %cmp = icmp uge i64 %a, %b
   br i1 %cmp, label %if.then, label %if.end
 
 if.then:                                          ; preds = %entry
   call void @func()
   br label %if.end
@@ skipping 27 matching lines @@
 ; OPTM1: jg
 ; OPTM1: jl
 ; OPTM1: jae
 ; OPTM1: call
 
 ; ARM32-LABEL: icmpGe64
 ; ARM32: cmp
 ; ARM32: cmpeq
 ; ARM32: movcs
 ; ARM32: movcc
-; ARM32: beq
 ; ARM32: bl
 ; ARM32: cmp
 ; ARM32: sbcs
 ; ARM32: movge
 ; ARM32: movlt
-; ARM32: beq
 ; ARM32: bl
 
 define internal void @icmpLt64(i64 %a, i64 %b, i64 %c, i64 %d) {
 entry:
   %cmp = icmp ult i64 %a, %b
   br i1 %cmp, label %if.then, label %if.end
 
 if.then:                                          ; preds = %entry
   call void @func()
   br label %if.end
@@ skipping 27 matching lines @@
 ; OPTM1: jl
 ; OPTM1: jg
 ; OPTM1: jb
 ; OPTM1: call
 
 ; ARM32-LABEL: icmpLt64
 ; ARM32: cmp
 ; ARM32: cmpeq
 ; ARM32: movcc
 ; ARM32: movcs
-; ARM32: beq
 ; ARM32: bl
 ; ARM32: cmp
 ; ARM32: sbcs
 ; ARM32: movlt
 ; ARM32: movge
-; ARM32: beq
 ; ARM32: bl
 
 define internal void @icmpLe64(i64 %a, i64 %b, i64 %c, i64 %d) {
 entry:
   %cmp = icmp ule i64 %a, %b
   br i1 %cmp, label %if.then, label %if.end
 
 if.then:                                          ; preds = %entry
   call void @func()
   br label %if.end
@@ skipping 27 matching lines @@
 ; OPTM1: jl
 ; OPTM1: jg
 ; OPTM1: jbe
 ; OPTM1: call
 
 ; ARM32-LABEL: icmpLe64
 ; ARM32: cmp
 ; ARM32: cmpeq
 ; ARM32: movls
 ; ARM32: movhi
-; ARM32: beq
 ; ARM32: bl
 ; ARM32: cmp
 ; ARM32: sbcs
 ; ARM32: movge
 ; ARM32: movlt
-; ARM32: beq
 ; ARM32: bl
 
 define internal i32 @icmpEq64Bool(i64 %a, i64 %b) {
 entry:
   %cmp = icmp eq i64 %a, %b
   %cmp.ret_ext = zext i1 %cmp to i32
   ret i32 %cmp.ret_ext
 }
 ; CHECK-LABEL: icmpEq64Bool
 ; CHECK: jne
@@ skipping 453 matching lines @@
   ret void
 }
 ; The following checks are not strictly necessary since one of the RUN
 ; lines actually runs the output through the assembler.
 ; CHECK-LABEL: icmpLt64Imm
 ; CHECK-NOT: cmp 0x{{[0-9a-f]+}},
 ; OPTM1-LABEL: icmpLt64Imm
 ; OPTM1-NOT: cmp 0x{{[0-9a-f]+}},
 ; ARM32-LABEL: icmpLt64Imm
 ; ARM32-NOT: cmp #{{[0-9a-f]+}},