Validator_ragel: REX prefix support in gen_dfa.py.

src/trusted/validator_ragel/gen_dfa.py

 #!/usr/bin/python
 # Copyright (c) 2012 The Native Client Authors. All rights reserved.
 # Use of this source code is governed by a BSD-style license that can be
 # found in the LICENSE file.
 
 import itertools
 import re
 import StringIO
 
 
@@ skipping 96 matching lines @@
     'att-show-name-suffix-q',
     'att-show-name-suffix-x',
     'att-show-name-suffix-y',
     'att-show-name-suffix-w',
 
     # Spurious REX.W bits (instructions 'in', 'out', 'nop', etc).
     'spurious-rex.w'
 ]
 
 
+def Attribute(name):
+  assert name in SUPPORTED_ATTRIBUTES
+  return name
+
+
 class Operand(object):
 
   __slots__ = [
       'read_write_attr',
       'arg_type',
       'size',
       'implicit',
       'index']
 
   # Operand read/write modes.
@@ skipping 53 matching lines @@
 
     TODO(shcherbina): it is possible that format will also be needed by
     validator64 in order to identify zero-extending instruction, but I'm not
     sure how it will be done.
 
     Returns:
       String like '8bit', '32bit', 'xmm', 'mmx', etc.
     """
     if self.size == 'b':
       return '8bit'
+    if self.size == 'w':
+      return '16bit'
+    if self.size == 'd':
+      return '32bit'
+    if self.size == 'q':
+      return '64bit'
     # TODO(shcherbina): support other formats.
     raise NotImplementedError()
 
   def __str__(self):
     return '%s%s%s%s' % (
         self.read_write_attr,
         self.arg_type,
         self.size,
         '*' if self.implicit else '')
 
 
 class Instruction(object):
 
   __slots__ = [
       'name',
       'operands',
       'opcodes',
-      'attributes']
+      'attributes',
+      'rex']
+
+  class RexStatus(object):
+    __slots__ = [
+        'b_matters',
+        'x_matters',
+        'r_matters',
+        'w_matters',
+        'w_set']
+
+  def __init__(self):
+    self.rex = self.RexStatus()
+    self.rex.b_matters = False
+    self.rex.x_matters = False
+    self.rex.r_matters = False
+    self.rex.w_matters = True
+    self.rex.w_set = False
 
   @staticmethod
   def Parse(line):
     """Parse one line of def file and return initialized Instruction object.
 
     Args:
       line: One line of def file (two or three columns separated by
           COLUMN_SEPARATOR). First column defines instruction name and operands,
           second one - opcodes and encoding details, third (optional)
           one - instruction attributes.
@@ skipping 104 matching lines @@
     """Return name in a form suitable to use as part of C identifier.
 
     In principle, collisions are possible, but will result in compilation,
     failure, so we are not checking for them here for simplicity.
 
     Returns:
       Instruction name with all non-alphanumeric characters replaced with '_'.
     """
     return re.sub(r'\W', '_', self.name)
 
+  def IsVexOrXop(self):
+    return len(self.opcodes) >= 3 and (
+        self.opcodes[0] == '0xc4' or
+        self.opcodes[0] == '0x8f' and self.opcodes[1] != '/0')

[khim, 2013/01/29 14:07:01]

I don't think you need to check self.opcodes[1] here.

"pop Er" is "0x8f /0" and "pop Ew" is "data16 0x8f /0"...

[Vlad Shcherbina, 2013/01/29 14:50:37]

Changed to what I think is more straightforward check.

+
   def __str__(self):
     return ' '.join([self.name] + map(str, self.operands))
 
 
 DECODER = object()
 VALIDATOR = object()
 
 
 class InstructionPrinter(object):
 
   def __init__(self, mode, bitness):
     assert mode in [DECODER, VALIDATOR]
     assert bitness in [32, 64]
     self._mode = mode
     self._bitness = bitness
     self._out = StringIO.StringIO()
 
   def GetContent(self):
     return self._out.getvalue()
 
+  def _PrintRexPrefix(self, instruction):

[halyavin, 2013/01/29 15:15:56]

"""Print machine for rex prefix."""

+    assert self._bitness == 64
+    assert not instruction.IsVexOrXop()
+
+    if Attribute('norex') in instruction.attributes:
+      return
+
+    if instruction.rex.w_set:
+      self._out.write('REXW_RXB\n')
+    else:
+      self._out.write('REX_RXB?\n')
+
   def _PrintOpcode(self, instruction):

[halyavin, 2013/01/29 15:15:56]

"""Print machine for opcode."""

     main_opcode_part = instruction.GetMainOpcodePart()
     if instruction.HasRegisterInOpcode():
       assert not instruction.HasModRM()
       assert not instruction.HasOpcodeInsteadOfImmediate()
 
       self._out.write(' '.join(main_opcode_part[:-1]))
 
       # Register is encoded in three least significant bits of the last byte
       # of the opcode (in 64-bit case REX.B bit also will be involved, but it
       # will be handled elsewhere).
@@ skipping 33 matching lines @@
       self._out.write('@operand%d_%s\n' % (i, operand.GetFormat()))
 
     # TODO(shcherbina): print operand sources and extract implicit operands.
 
     # TODO(shcherbina): print '@last_byte_is_not_immediate' when approptiate.
     # TODO(shcherbina): print '@modifiable_instruction' in validator64 if
     # attribute 'nacl-amd64-modifiable' is present.
     # TODO(shcherbina): print info about CPU features.
     # TODO(shcherbina): att_show_name_suffix.
 
-    # TODO(shcherbina): print spurious REX stuff (probably not in this
-    # function).
+    if (self._mode == DECODER and
+        self._bitness == 64 and
+        not instruction.IsVexOrXop()):
+      # Note that even if 'norex' attribute is present, we print
+      # @spurious_rex_... actions because NOP needs them (and it has REX
+      # prefix specified as part of the opcode).
+      # TODO(shcherbina): fix that?
+      if not instruction.rex.b_matters:
+        self._out.write('@set_spurious_rex_b\n')
+      if not instruction.rex.x_matters:
+        self._out.write('@set_spurious_rex_x\n')
+      if not instruction.rex.r_matters:
+        self._out.write('@set_spurious_rex_r\n')
+      if not instruction.rex.w_matters:
+        self._out.write('@set_spurious_rex_w\n')
 
   def _PrintOperandSource(self, operand, source):
     # TODO(shcherbina): add mechanism to check that all operand sources are
     # printed.
     self._out.write('@operand%d_%s\n' % (operand.index, source))
 
   def _PrintImplicitOperandSources(self, instruction):
     """Print actions specifying sources of implicit operands.
 
     Args:
       instruction: instruction.
 
     Returns:
       None.
     """
     operand = instruction.FindOperand('a')
     if operand is not None:
       self._PrintOperandSource(operand, 'rax')
     # TODO(shcherbina): handle other implicit operands.
 
   def PrintInstructionWithoutModRM(self, instruction):
     # TODO(shcherbina): print legacy prefixes.
-    # TODO(shcherbina): print REX prefix.
 
+    assert not instruction.IsVexOrXop()

[khim, 2013/01/29 14:07:01]

Why not? Where and how do you plan to print vzeroall, vzeroupper, etc?

[Vlad Shcherbina, 2013/01/29 14:50:37]

Right, marked as 'not implemented'.

     assert not instruction.HasModRM()
+
+    if self._bitness == 64:
+      self._PrintRexPrefix(instruction)
+
     assert not instruction.HasOpcodeInsteadOfImmediate(), 'not supported yet'
 
     self._PrintOpcode(instruction)
     self._out.write('\n')
 
     self._PrintSignature(instruction)
     self._PrintImplicitOperandSources(instruction)
 
     # TODO(shcherbina): print immediate args.
 
@@ skipping 87 matching lines @@
 
   return result
 
 
 def main():
   pass
 
 
 if __name__ == '__main__':
   main()